PCM1606E Datasheet, PDF (9/28 Pages) Texas Instruments – 24-Bit, 192-kHz SAMPLING. 6-CHANNEL, ENHANCED MULTILEVEL, DELTA- SIGMA DIGITAL-TO-ANALOG CONVERTER

PCM1606
timing requirements (continued)
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
BCK
t(BCKH)
t(BCKL)
Bit Clock Pulse
Cycle Time†
2.0 V
0.8 V
PARAMETERS
t(BCKH) Bit clock pulse duration HIGH
t(BCKL) Bit clock pulse duration LOW
† _{1/128 fS, 1/256 fS, and 1/512 fS.}
Figure 4. Bit Clock Timing for TDM Format
MIN MAX UNIT
10
ns
10
ns
t(BCY)
t(BCH)
t(BCL)
t(BL)
t(LB)
tsu(D)
th(D)
LRCK
BCK
t(BCH)
t(BCL)
t(BCY)
t(BL)
t(LB)
DATA1
tsu(D)
th(D)
PARAMETER
BCK pulse cycle time
BCK high-level time
BCK low-level time
BCK rising edge to LRCK edge
LRCK falling edge to BCK rising edge
DATA setup time
DATA hold time
Figure 5. Audio Interface Timing for TDM Format
1.4 V
1.4 V
1.4 V
MIN MAX
20
10
10
7
7
7
7
UNIT
ns
ns
ns
ns
ns
ns
ns
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