OPA2111 Datasheet, PDF (9/15 Pages) Burr-Brown (TI) – Dual Low Noise Precision Difet OPERATIONAL AMPLIFIER

GUARDING AND SHIELDING
As in any situation where high impedances are involved,
careful shielding is required to reduce “hum” pickup in input
leads. If large feedback resistors are used, they should also
be shielded along with the external input circuitry.
Leakage currents across printed circuit boards can easily
exceed the bias current of the OPA2111. To avoid leakage
problems, it is recommended that the signal input lead of the
OPA2111 be wired to a Teflon standoff. If the OPA2111 is
to be soldered directly into a printed circuit board, utmost
care must be used in planning the board layout. A “guard”
pattern should completely surround the high impedance
input leads and should be connected to a low impedance
point which is at the signal input potential (see Figure 2).
NOISE: FET vs BIPOLAR
Low noise circuit design requires careful analysis of all
noise sources. External noise sources can dominate in many
cases, so consider the effect of source resistance on overall
operational amplifier noise performance. At low source
impedances, the low voltage noise of a bipolar operational
amplifier is superior, but at higher impedances the high
current noise of a bipolar amplifier becomes a serious
liability. Above about 15kΩ the OPA2111 will have lower
total noise than an OP-27 (see Figure 3).
BIAS CURRENT CHANGE
vs COMMON-MODE VOLTAGE
The input bias currents of most popular BIFET® opera-
tional amplifiers are affected by common-mode voltage
(Figure 4). Higher input FET gate-to-drain voltage causes
leakage and ionization (bias) currents to increase. Due to its
cascode input stage, the extremely low bias current of the
OPA2111 is not compromised by common-mode voltage.
Non-Inverting
Buffer
APPLICATIONS CIRCUITS
Figures 5 through 13 are circuit diagrams of various appli-
cations for the OPA2111.
1k
E_O
OP-27 + Resistor
OPA2111 + Resistor
Resistor Noise Only
100
R_S
10
1
100
E_O = e_N2 + (i_NR_S)² + 4kTR_S
OPA2111 + Resistor
Resistor Noise Only
OP-27 + Resistor
BM
1k
10k
100k
1M
10M
Source Resistance, R_S (Ω)
FIGURE 3. Voltage Noise Spectral Density vs Source
Resistance.
80
T_A = 25°C; curves taken from
60 _{manufacturers' published}
typical data
40
LF156/157
20
LF155
AD547
0
OPA2111
OP-15/16/17 “Perfect Bias Current Cancellation”
–20
–15
–10
–5
0
5
10
15
Common-Mode Voltage (VDC)
FIGURE 4. Input Bias Currrent vs Common-Mode Voltage.
2
A
1 ^Out
2
A
1 ^Out
In
3
In
3
Inverting
In
2
1 ^Out
A
3
TO-99 Bottom View
4
3
5
2
6
1
7
8
Board layout for input guarding: guard top and bottom of board.
Alternate: use Teflon^® standoff for sensitive input pins.
Teflon^® E. I. Du Pont de Nemours & Co.
FIGURE 2. Connection of Input Guard.
1MΩ
In Operate ^10kΩ
Zero
2
1/2
1
OPA2111BM
3
Out
100kΩ
100Ω
100kΩ
Polypropylene
1µF
6
7
1/2
OPA2111BM
5
Gain = –100
V_OS ≤ 5µV
Drift ≤ 0.028µV/°C
Zero Droop ≤ 2µV/s
Referred to Input
FIGURE 5. Auto-Zero Amplifier.
®
9
OPA2111