LP8725 Datasheet, PDF(9/46 Page) National Semiconductor (TI) – Power Management Unit for Application/Multimedia Processors and Sub-Systems

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LP8725 Datasheet, PDF (9/46 Pages) National Semiconductor (TI) – Power Management Unit for Application/Multimedia Processors and Sub-Systems

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LP8725

www.ti.com

SNVS618G â DECEMBER 2009 â REVISED MAY 2013

Figure 5. LP8725 Startup and Shutdown Sequence if CONFIG=VIN1 Note 1, Note 2

START UP sequence

Timing Code

012345 6

SHUT DOWN sequence

is in reverse order of START UP sequence

Timing Code

6543210

PWR_ON

PS_HOLD

Buck 1

Buck 2

LDO1

Buck 1

Buck 2

LDO1

LDO2

LDO3

LDO4

LDO5

LILO 1

LILO 2

tON

tS tS tS tS tS tS

tOFF

tS tS tS tS tS tS

LILO 2

Note 4

START UP

IDLE

SHUT DOWN

All timing is typical.

tON/OFF 30 ms typ. de-bounce times

tS Programmable time steps. (Typically 64 Âµs/step.) Time step accuracy is defined by OSC frequency accuracy.

Note 1 STARTUP and SHUTDOWN sequences are defined by registers. Sequences given here are valid if there the

registers are not rewritten via Serial Interface.

Note 2 The timing showed here define time points when LDOs and BUCK are enabled/disabled. Enabling /disabling

process duration depends on voltages and loading conditions. Buck startup duration is typically 170 Âµs. LDO startup

duration is typically 35 Âµs. For details please see LDOs and BUCK Electrical Specifications.

Note 4 At this time point registers are reset to POR default values.

Product Folder Links: LP8725

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