LP3881 Datasheet, PDF (9/18 Pages) National Semiconductor (TI) – 0.8A Fast-Response Ultra Low Dropout Linear Regulators

LP3881
www.ti.com
SNVS224F – MARCH 2003 – REVISED APRIL 2013
• C is the value of capacitance
(1)
The pole frequency is:
F_p = 1 / (2 X π X R_L X C)
where
• R_L is the load resistance connected to the regulator output
(2)
To understand why a small capacitor can reduce phase margin: assume a typical LDO with a bandwidth of
1MHz, which is delivering 0.5A of current from a 2.5V output (which means R_L is 5 Ohms). We then place a .047
µF capacitor on the output. This creates a pole whose frequency is:
F_p = 1 / (2 X π X 5 X .047 X 10E-6) = 677 kHz
(3)
This pole would add close to 60 degrees of phase lag at the crossover (unity gain) frequency of 1 MHz, which
would almost certainly make this regulator oscillate. Depending on the load current, output voltage, and
bandwidth, there are usually values of small capacitors which can seriously reduce phase margin. If the
capacitors are ceramic, they tend to oscillate more easily because they have very little internal inductance to
damp it out. If bypass capacitors are used, it is best to place them near the load and use trace inductance to
"decouple" them from the regulator output.
INPUT CAPACITOR
The input capacitor must be at least 4.7 µF, but can be increased without limit. It's purpose is to provide a low
source impedance for the regulator input. Ceramic capacitors work best for this, but Tantalums are also very
good. There is no ESR limitation on the input capacitor (the lower, the better). Aluminum electrolytics can be
used, but their ESR increase very quickly at cold temperatures. They are not recommended for any application
where temperatures go below about 10°C.
BIAS CAPACITOR
The 0.1µF capacitor on the bias line can be any good quality capacitor (ceramic is recommended).
BIAS VOLTAGE
The bias voltage is an external voltage rail required to get gate drive for the N-FET pass transistor. Bias voltage
must be in the range of 4.5 - 6V to assure proper operation of the part.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the regulator output from turning on if the bias voltage
is below approximately 4V.
SHUTDOWN OPERATION
Pulling down the shutdown (S/D) pin will turn-off the regulator. Pin S/D must be actively terminated through a
pull-up resistor (10 kΩ to 100 kΩ) for a proper operation. If this pin is driven from a source that actively pulls high
and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to Vin
if not used.
POWER DISSIPATION/HEATSINKING
A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of
the application. Under all possible conditions, the junction temperature must be within the range specified under
operating conditions. The total power dissipation of the device is given by:
P_D = (V_IN−V_OUT)I_OUT+ (V_IN)I_GND
where
• I_GND is the operating ground current of the device
(4)
The maximum allowable temperature rise (T_Rmax) depends on the maximum ambient temperature (T_Amax) of the
application, and the maximum allowable junction temperature (T_Jmax):
T_Rmax = T_Jmax− T_Amax
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