LMX2491 Datasheet, PDF (9/31 Pages) Texas Instruments – 6.4-GHz Low Noise RF PLL With Ramp/Chirp Generation

www.ti.com
LMX2491
SNAS711 – OCTOBER 2016
The resistor and the charge pump current are changed simultaneously so that the phase margin remains the
same while the loop bandwidth is by a factor of K as shown in the following table:
FL_CPG
K
R2pLF
Table 3. Suggested Equations to Calculate R2pLF
PARAMETER
Charge Pump Gain in Fastlock
Loop Bandwidth Multiplier
External Resistor
CALCULATION
Typically use the highest value.
K=sqrt(FL_CPG/CPG)
R2 / (K-1)
Cycle slip reduction is another method that can also be used to speed up lock time by reducing cycle slipping.
Cycle slipping typically occurs when the phase detector frequency exceeds about 100x the loop bandwidth of the
PLL. Cycle slip reduction works in a different way than fastlock. To use this, the phase detector frequency is
decreased while the charge pump current is simultaneously increased by the same factor. Although the loop
bandwidth is unchanged, the ratio of the phase detector frequency to the loop bandwidth is, and this is helpful for
cases when the phase detector frequency is high. Because cycle slip reduction changes the phase detector rate,
it also impacts other things that are based on the phase detector rate, such as the fastlock timeout-counter and
ramping controls.
7.3.9 Lock Detect and Charge Pump Voltage Monitor
The LMX2491 offers two methods to determine if the PLL is in lock: charge pump voltage monitoring and digital
lock detect. These features can be used individually or in conjunction to give a reliable indication of when the
PLL is in lock. The output of this detection can be routed to the TRIG1, TRIG2, MOD, or MUXout terminals.
7.3.9.1 Charge Pump Voltage Monitor
The charge pump voltage monitor allows the user to set low (CMP_THR_LOW) and high (CMP_THR_HIGH)
thresholds for a comparator that monitors the charge pump output voltage.
Table 4. Desired Comparator Threshold Register Settings for Two Charge Pump Supplies
V_CP
3.3 V
5.0 V
THRESHOLD
CPM_THR_LOW
= (Vthresh + 0.08) / 0.085
CPM_THR_HIGH
= (Vthresh - 0.96) / 0.044
CPM_THR_LOW
= (Vthresh + 0.056) / 0.137
CPM_THR_HIGH
= (Vthresh -1.23) / 0.071
SUGGESTED LEVEL
6 for 0.5-V limit
42 for 2.8-V limit
4 for 0.5-V limit
46 for 4.5-V limit
7.3.9.2 Digital Lock Detect
Digital lock detect works by comparing the phase error as presented to the phase detector. If the phase error
plus the delay as specified by the PFD_DLY bit is outside the tolerance as specified by DLD_TOL, then this
comparison would be considered to be an error, otherwise passing. The DLD_ERR_CNT specifies how may
errors are necessary to cause the circuit to consider the PLL to be unlocked. The DLD_PASS_CNT specifies
how many passing comparisons are necessary to cause the PLL to be considered to be locked and also resets
the count for the errors. The DLD_TOL value should be set to no more than half of a phase detector period plus
the PFD_DLY value. The DLD_ERR_CNT and DLD_PASS_CNT values can be decreased to make the circuit
more sensitive. If the circuit is too sensitive, then chattering can occur and the DLD_ERR_CNT,
DLD_PASS_CNT, or DLD_TOL values should be increased.
NOTE
If the OSCin signal goes away and there is no noise or self-oscillation at the OSCin pin,
then it is possible for the digital lock detect to indicate a locked state when the PLL really
is not in lock. If this is a concern, then digital lock detect can be combined with charge
pump voltage monitor to detect this situation.
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: LMX2491
Submit Documentation Feedback
9