LMR14030 Datasheet, PDF (9/30 Pages) Texas Instruments – LMR14030 SIMPLE SWITCHER® 40 V 3.5 A, 2.2 MHz Step-Down Converter with 40 μA IQ

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LMR14030
SNVSA81A – FEBRUARY 2015 – REVISED APRIL 2015
8.3 Feature Description
8.3.1 Fixed Frequency Peak Current Mode Control
The following operation description of the LMR14030 will refer to the Function Block Diagram and to the
waveforms in Figure 13. LMR14030 output voltage is regulated by turning on the high-side N-MOSFET with
controlled ON time. During high-side switch ON time, the SW pin voltage swings up to approximately V_IN, and the
inductor current i_L increase with linear slope (V_IN – V_OUT) / L. When high-side switch is off, inductor current
discharges through freewheel diode with a slope of –V_OUT / L. The control parameter of Buck converter is defined
as Duty Cycle D = t_ON /T_SW, where t_ON is the high-side switch ON time and T_SW is the switching period. The
regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In an ideal Buck
converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to the input
voltage: D = V_OUT / V_IN.
VSW
VIN
D = tON/ TSW
0
-VD
iL
ILPK
IOUT
tON
tOFF
TSW
t
ûiL
t
0
Figure 13. SW Node and Inductor Current Waveforms in
Continuous Conduction Mode (CCM)
The LMR14030 employs fixed frequency peak current mode control. A voltage feedback loop is used to get
accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak
inductor current is sensed from the high-side switch and compared to the peak current to control the ON time of
the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer external
components, makes it easy to design, and provides stable operation with almost any combination of output
capacitors. The regulator operates with fixed switching frequency at normal load condition. At very light load, the
LMR14030 will operate in Sleep-mode to maintain high efficiency and the switching frequency will decrease with
reduced load current.
8.3.2 Slope Compensation
The LMR14030 adds a compensating ramp to the MOSFET switch current sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycle greater than 50%. The peak current limit of the
high-side switch is not affected by the slope compensation and remains constant over the full duty cycle range.
8.3.3 Sleep-mode
The LMR14030 operates in Sleep-mode at light load currents to improve efficiency by reducing switching and
gate drive losses. If the output voltage is within regulation and the peak switch current at the end of any
switching cycle is below the current threshold of 300 mA, the device enters Sleep-mode. The Sleep-mode current
threshold is the peak switch current level corresponding to a nominal internal COMP voltage of 400 mV.
When in Sleep-mode, the internal COMP voltage is clamped at 400mV and the high-side MOSFET is inhibited,
and the device draws only 40 μA (typical) input quiescent current. Since the device is not switching, the output
voltage begins to decay. The voltage control loop responds to the falling output voltage by increasing the internal
COMP voltage. The high-side MOSFET is enabled and switching resumes when the error amplifier lifts internal
COMP voltage above 400 mV. The output voltage recovers to the regulated value, and internal COMP voltage
eventually falls below the Sleep-mode threshold at which time the device again enters Sleep-mode.
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