DAC8830-EP_16 Datasheet, PDF (9/32 Pages) Texas Instruments – 16-Bit, Ultra-Low Power, Voltage-Output Digital-to-Analog Converters

DAC8830-EP
DAC8831-EP
www.ti.com
SGLS334C – AUGUST 2006 – REVISED APRIL 2007
TIMING CHARACTERISTICS: V_DD = 5 V^{(1) (2)}
At –55°C to 125°C (unless otherwise noted)
t_sck
t_wsck
t_Delay
t_Lead
t_Lag
t_DSCLK
t_td
t_su
t_ho
t_WLDAC
t_DLDAC
PARAMETER
SCLK period
SCLK high or low time
Delay from SCLK high to CS low
CS enable lead time
CS enable lag time
Delay from CS high to SCLK high
CS high between active period
Data setup time (input)
Data hold time (input)
LDAC width
Delay from CS high to LDAC low
V_DD high to CS low (power-up delay)
MIN
MAX UNIT
20
ns
10
ns
18
ns
12
ns
15
ns
15
ns
30
ns
10
ns
0
ns
30
ns
30
ns
10
μs
(1) Specified by design. Not production tested.
(2) Sample tested during the initial release and after any redesign or process changes that may affect this parameter.
TIMING CHARACTERISTICS: V_DD = 3 V^{(1) (2)}
At –55°C to 125°C (unless otherwise noted)
t_sck
t_wsck
t_Delay
t_Lead
t_Lag
t_DSCLK
t_td
t_su
t_ho
t_WLDAC
t_DLDAC
PARAMETER
SCLK period
SCLK high or low time
Delay from SCLK high to CS low
CS enable lead time
CS enable lag time
Delay from CS high to SCLK high
CS high between active period
Data setup time (input)
Data hold time (input)
LDAC width
Delay from CS high to LDAC low
V_DD high to CS low (power-up delay)
MIN
MAX
20
10
18
15
15
15
30
10
0
30
30
10
(1) Specified by design. Not production tested.
(2) Sample tested during the initial release and after any redesign or process changes that may affect this parameter.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
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