CSD95373AQ5M Datasheet, PDF (9/25 Pages) Texas Instruments – Synchronous Buck NexFET Power Stage

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CSD95373AQ5M
SLPS458 – DECEMBER 2013
ENABLE
The ENABLE pin is TTL compatible. The logic level thresholds are sustained under all V_DD operating conditions
between V_POR to V_DD. In addition, if this pin is left floating, a weak internal pulldown resistor of 100 kΩ pulls the
ENABLE pin below the logic level low threshold. The operational functions of this pin should follow the timing
diagram outlined in Figure 15. A logic level low actively holds both Control FET and Sync FET gates low and V_DD
pin should typically draw less than 5 µA.
90%
t_PDL
ENABLE
t_PDH
10%
90%
V_SW
10%
T0488-01
Figure 15. CSD95373AQ5M ENABLE Timing Diagram (V_DD = PWM = 5V)
POWER UP SEQUENCING
If the ENABLE signal is used, it is necessary to ensure proper co-ordination with the ENABLE and soft-start
features of the external PWM controller in the system. If the CSD95373AQ5M was disabled through ENABLE
without sequencing with the PWM IC controller, the buck converter output will have no voltage or fall below
regulation set point voltage. As a result, the PWM controller IC delivers Max duty cycle on the PWM line. If the
Power Stage is re-enabled by driving the ENABLE pin high, there will be an extremely large input inrush current
when the output voltage builds back up again. The input inrush current might have undesirable consequences
such as inductor saturation, driving the input power supply into current limit or even catastrophic failure of the
CSD95373AQ5M device. Disabling the PWM controller is recommended when the CSD95373AQ5M is disabled.
The PWM controller should always be re-enabled by going through soft-start routine to control and minimize the
input inrush current and reduce current and voltage stress on all buck converter components. TI recommends
that the external PWM controller be disabled when CSD95373AQ5M is disabled or nonoperational because of
UVLO.
When ENABLE signal is toggled, there is an internal 3 µs hold-off time before the driver responds to PWM
events to ensure the analog sensing circuitry is properly powered and stable. This hold-off time should be
considered when designing the power-up sequencing of the controller IC and the Power Stage.
PWM
The input PWM pin incorporates a 3-state function. The Control FET and Sync FET gates are forced low if the
PWM pin is left floating for more than the 3-state Hold off time (t_3HT). The 3-state mode can be entered by
actively driving the PWM input to the V_T3 voltage, or the PWM input can be made high impedance and internal
current sources drive PWM to V_T3. The PWM input can source up to I_PWMH and sink down to I_PWML current to
drive PWM to the V_T3 voltage, but consumes no current when sitting at the V_T3 voltage. Operation in and out of
3-state mode should follow the timing diagram outlined in Figure 16. Both V_PWML and V_PWMH threshold levels are
set to accommodate both 3.3 V and 5 V logic controllers. During typical operation, the PWM signal should be
driven to logic levels Low and High with a maximum of 500 Ω sink/source impedance respectively.
Copyright © 2013, Texas Instruments Incorporated
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