CDCVF2510A_15 Datasheet, PDF (9/18 Pages) Texas Instruments – 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

CDCVF2510A
www.ti.com ............................................................................................................................................... SCAS764C – MARCH 2004 – REVISED FEBRUARY 2009
TYPICAL CHARACTERISTICS
STATIC PHASE ERROR
vs
LOAD CAPACITANCE
600
V_CC = 3.3 V
f_c = 100 MHz
400
C_(LY1−n) = 25 pF || 500 Ω
T_A = 25°C
See Notes A, B, and C
STATIC PHASE ERROR
vs
LOAD CAPACITANCE
600
V_CC = 3.3 V
f_c = 133 MHz
400
C_(LY1−n) = 25 pF || 500 Ω
T_A = 25°C
See Notes A, B, and C
200
CLK to Y1−n
0
200
CLK to Y1−n
0
−200
−400
CLK to FBOUT
−600
3
8 13 18 23 28 33 38
C_(LF) − Load Capacitance − pF
Figure 4.
0
−50
−100
STATIC PHASE ERROR
vs
SUPPLY VOLTAGE AT FBOUT
f_c = 133 MHz
C_(LY) = 25 pF || 500 Ω
C_(LF) = 12 pF || 500 Ω
T_A = 25°C
See Notes A, B, and C
−150
−200
CLK to FBOUT
−250
−300
−350
−400
3
3.1 3.2
3.3
3.4
3.5
3.6
V_CC − Supply Voltage at FBOUT − V
Figure 6.
A. Trace length FBOUT to FBIN = 5 mm, Z_O = 50Ω
B. C_(LY) = Lumped capacitive load Y_1-n
C. C_(LFx) = Lumped feedback capacitance at FBOUT = FBIN
−200
−400
CLK to FBOUT
−600
3
8 13 18 23 28 33 38
C_(LF) − Load Capacitance − pF
Figure 5.
0
−50
−100
STATIC PHASE ERROR
vs
CLOCK FREQUENCY
V_CC = 3.3 V
C_(LY) = 25 pF || 500 Ω
C_(LF) = 12 pF || 500 Ω
T_A = 25°C
See Notes A, B, and C
−150
−200
CLK to FBOUT
−250
−300
−350
−400
50
75 100 125 150 175 200
f_c − Clock Frequency − MHz
Figure 7.
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