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BQ34Z651_15 Datasheet, PDF (9/29 Pages) Texas Instruments – SBS 1.1-Compliant Gas Gauge | |||
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bq34z651
www.ti.com
SLUSAL7 â AUGUST 2011
ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range (unless otherwise noted), TA = â40°C to 85°C, V(REG25) = 2.41 V to 2.59 V,
V(BAT) = 14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LED OUTPUTS
VOL
Output low voltage
VCELL+ HIGH VOLTAGE TRANSLATION
LED1, LED2, LED3, LED4, LED5
0.4
V
V(VCELL+OUT)
V(VCELL+REF) Translation output
V(VCELL+PACK)
V(VCELL+BAT)
CMMR
Common mode rejection ratio
VC(n) â VC(n+1) = 0 V;
TA = â40°C to 100°C
VC(n) â VC(n+1) = 4.5 V;
TA = â40°C to 100°C
Internal AFE reference voltage;
TA = â40°C to 100°C
Voltage at PACK pin;
TA = â40°C to 100°C
Voltage at BAT pin;
TA = â40°C to 100°C
VCELL+
0.950
0.975
1
0.275
0.3
0.375
0.965
0.975
0.985
V
0.98 Ã
V(PACK)/18
V(PACK)/18
1.02 Ã
V(PACK)/18
0.98 Ã
V(BAT)/18
V(BAT)/18
1.02 Ã
V(BAT)/18
40
dB
K
Cell scale factor
K= {VCELL+ output (VC5=0 V; VC4=4.5
V) â VCELL+ output (VC5 = 0 V; VC4 =0
V)}/4.5
K= {VCELL+ output (VC2 = 13.5 V; VC1
= 18 V) â VCELL+ output
(VC5 = 13.5 V; VC1 = 13.5 V)}/4.5
0.147
0.147
0.150
0.150
0.153
0.153
I(VCELL+OUT) Drive Current to VCELL+ capacitor
VC(n) â VC(n+1) = 0 V; VCELL+ = 0 V;
TA = â40°C to 100°C
12
18
V(VCELL+O)
CELL offset error
CELL output (VC2 = VC1 = 18 V) â CELL
output (VC2 = VC1 = 0 V)
â18
â1
μA
18
mV
IVCnL
VC(n) pin leakage current
CELL BALANCING
VC1, VC2, VC3, VC4, VC5 = 3 V
â1
0.01
1
μA
RBAL
Internal cell balancing FET resistance
RDS(on) for internal FET switch at
VDS = 2 V; TA = 25°C
200
400
600
â¦
HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; TA = 25°C (unless otherwise noted)
V(OL)
OL detection threshold voltage
accuracy
VOL = 25 mV (min)
VOL = 100 mV; RSNS = 0, 1
VOL = 205 mV (max)
15
25
90
100
185
205
35
110
mV
225
V(SCC)
SCC detection threshold voltage
accuracy
V(SCC) = 50 mV (min)
V(SCC) = 200 mV; RSNS = 0, 1
V(SCC) = 475 mV (max)
30
50
180
200
428
475
70
220
mV
523
V(SCD)
SCD detection threshold voltage
accuracy
V(SCD) = â50 mV (min)
V(SCD) = â200 mV; RSNS = 0, 1
V(SCD) = â475 mV (max)
â30
â50
â70
â180
â200
â220
mV
â428
â475
â523
tda
Delay time accuracy
±15.25
μs
tpd
Protection circuit propagation delay
50
μs
FET DRIVE CIRCUIT; TA = 25°C (unless otherwise noted)
V(DSGON)
DSG pin output on voltage
V(DSGON) = V(DSG) â V(PACK);
V(GS) = 10 Mâ¦; DSG and CHG on;
TA = â40°C to 100°C
8
12
16
V
V(CHGON)
CHG pin output on voltage
V(CHGON) = V(CHG) â V(BAT);
V(GS) = 10 Mâ¦; DSG and CHG on;
TA = â40°C to 100°C
8
12
16
V
V(DSGOFF)
DSG pin output off voltage
V(DSGOFF) = V(DSG) â V(PACK)
0.2
V
V(CHGOFF)
CHG pin output off voltage
V(CHGOFF) = V(CHG) âV(BAT)
0.2
V
tr
Rise time
CL= 4700 pF; V(PACK) ⤠DSG ⤠V(PACK) +
4V
CL= 4700 pF; V(BAT) ⤠CHG ⤠V(BAT) + 4 V
400
1000
μs
400
1000
tf
Fall time
CL= 4700 pF; V(PACK) + V(DSGON) ⤠DSG â¤
V(PACK) + 1 V
CL= 4700 pF; V(BAT) + V(CHGON) ⤠CHG â¤
V(BAT) + 1 V
40
200
μs
40
200
Copyright © 2011, Texas Instruments Incorporated
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