BQ24751B Datasheet, PDF (9/38 Pages) Texas Instruments – Host-Controlled Multi-Chemistry Battery Charger with Low Iq and System Power Selector

Not Recommended For New Designs
bq24751B
www.ti.com .......................................................................................................................................................... SLUS835A – JULY 2008 – REVISED MARCH 2009
ELECTRICAL CHARACTERISTICS (continued)
7 V ≤ V_PVCC ≤ 24 V, 0°C < T_J < 125°C, typical values are at T_A = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
AC SWITCH (ACDRV) DRIVER
R_{DS(off)_AC}
R_{DS(on)_AC}
V_{/ACDRV_REG}
ACFET turn-off resistance
ACFET turn-on resistance
ACFET drive voltage
ACFET Power-up Delay
AC / BAT MOSFET DRIVERS TIMING
V_PVCC > 5 V
V_PVCC > 5 V
V_{/ACDRV_REG} = V_PVCC – V_ACDRV when
V_PVCC > 5 V and ACFET is on
Delay to turn on ACFET after adapter is detected
(after V_ACDET > 2.4 V)
80
Ω
2.5
kΩ
6.5
V
518 700
908
ms
Driver dead time
Dead time when switching between ACDRV and
BATDRV
10
µs
PWM HIGH SIDE DRIVER (HIDRV)
R_{DS(on)_HI}
R_{DS(off)_HI}
V_{BTST_REFRESH}
High side driver turn-on resistance
High side driver turn-off resistance
Bootstrap refresh comparator threshold
voltage
V_BTST – V_PH = 5.5 V, tested at 100 mA
V_BTST – V_PH = 5.5 V, tested at 100 mA
V_BTST – V_PH when low side refresh pulse is
requested
3
6
Ω
0.7
1.4
Ω
4
V
PWM LOW SIDE DRIVER (LODRV)
R_{DS(on)_LO}
Low side driver turn-on resistance
R_{DS(off)_LO}
Low side driver turn-off resistance
PWM DRIVERS TIMING
REGN = 6 V, tested at 100 mA
REGN = 6 V, tested at 100 mA
3
6
Ω
0.6
1.2
Ω
Driver Dead Time — Dead time when
switching between LODRV and HIDRV.
No load at LODRV and HIDRV
30
ns
PWM OSCILLATOR
F_SW
PWM switching frequency
V_{RAMP_HEIGHT}
PWM ramp height
QUIESCENT CURRENT
As percentage of PVCC
240 300
6.6
360
kHz
%PVCC
I_{OFF_STATE}
Total off-state quiescent current into
pins SRP, SRN, BAT, BTST, PH,
PVCC, ACP, ACN
V_BAT = 16.8 V, V_ACDET < 0.6 V,
V_PVCC > 5 V, T_J = 0 to 85°C
7
10
µA
I_{BATQ_CD}
Total quiescent current into pins: SRP,
SRN, BAT, BTST, PH
Adapter present, V_ACDET > 2.4 V, charge disabled
100
200
µA
I_AC
Adapter quiescent current
INTERNAL SOFT START (8 steps to regulation current)
V_PVCC = 20 V, charge disabled
1
1.5
mA
Soft start steps
8
step
Soft start step time
1.7
ms
CHARGER SECTION POWER-UP SEQUENCING
Charge-enable delay after power-up
Delay from when adapter is detected to when the
charger is allowed to turn on
518 700
908
ms
LOGIC INPUT PIN CHARACTERISTICS (CHGEN, LEARN)
V_{IN_LO}
Input low threshold voltage
V_{IN_HI}
Input high threshold voltage
I_BIAS
Input bias current
t_{CHGEN_DEGLITCH}
Charge enable deglitch time
LOGIC INPUT PIN CHARACTERISTICS (CELLS)
V_CHGEN = 0 to V_REGN
ACDET > 2.4 V, CHGEN rising
0.8
V
2.1
1
µA
2
ms
V_{IN_LO}
V_{IN_MID}
Input low threshold voltage, 3 cells
Input mid threshold voltage, 2 cells
CELLS voltage falling edge
CELLS voltage rising for MIN,
CELLS voltage falling for MAX
0.5
0.8
1.8
V
V_{IN_HI}
I_{BIAS_FLOAT}
Input high threshold voltage, 4 cells
Input bias float current for 2-cell
selection
CELLS voltage rising
V_CHGEN = 0 to V_REGN
2.5
–1
1
µA
OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS (ACGOOD)
V_{OUT_LO}
Output low saturation voltage
Delay, ACGOOD falling
Sink Current = 5 mA
0.5
V
518 700
908
ms
Delay, ACGOOD rising
7
9
11
ms
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24751B
Submit Documentation Feedback
9