BQ20Z655 Datasheet, PDF (9/23 Pages) Texas Instruments – SBS 1.1-COMPLIANT GAS GAUGE AND PROTECTION ENABLED WITH IMPEDANCE TRACK

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SLUSAH8 – APRIL 2011
ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range (unless otherwise noted), T_A = –40°C to 85°C, V_(REG25) = 2.41 V to 2.59 V,
V_(BAT) = 14 V, C_(REG25) = 1 µF, C_(REG33) = 2.2 µF; typical values at T_A = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
V_(SCC)
V_(SCD)
t_da
t_pd
SCC detection threshold
voltage accuracy
SCD detection threshold
voltage accuracy
Delay time accuracy
Protection circuit propagation
delay
V_(SCC) = 50 mV (min)
V_(SCC) = 200 mV; RSNS = 0, 1
V_(SCC) = 475 mV (max)
V_(SCD) = –50 mV (min)
V_(SCD) = –200 mV; RSNS = 0, 1
V_(SCD) = –475 mV (max)
30
50
70
180
200
220
mV
428
475
523
–30
–50
–70
–180
–200
–220
mV
–428
–475
–523
±15.25
μs
50
μs
FET DRIVE CIRCUIT; T_A = 25°C (unless otherwise noted)
V_(DSGON)
DSG pin output on voltage
V_(DSGON) = V_(DSG) - V_(PACK);
V_(GS) connected to 10 MΩ; DSG and CHG on;
T_A = –40°C to 100°C
8
12
16
V
V_(CHGON)
CHG pin output on voltage
V_(CHGON) = V_(CHG) - V_(BAT);
V_(GS) = 10 MΩ; DSG and CHG on;
T_A = –40°C to 100°C
8
12
16
V
V_(DSGOFF)
DSG pin output off voltage
V_(DSGOFF) = V_(DSG) - V_(PACK)
0.2
V
V_(CHGOFF)
CHG pin output off voltage
V_(CHGOFF) = V_(CHG) - V_(BAT)
0.2
V
t_r
Rise time
C_L= 4700 pF
V_(CHG): V_(PACK) ≥ V_(PACK) + 4V
V_(DSG): V_(BAT) ≥V_(BAT) + 4V
400
1000
μs
400
1000
t_f
Fall time
C_L= 4700 pF
V_(CHG): V_(PACK) + V_(CHGON) ≥ V_(PACK)+
1V
V_(DSG): VC1 + V_(DSGON) ≥ VC1 + 1 V
40
200
μs
40
200
V_(ZVCHG)
ZVCHG clamp voltage
BAT = 4.5 V
3.3
3.5
3.7
V
LOGIC; T_A = –40°C to 100°C (unless otherwise noted)
R_(PULLUP)
Internal pullup resistance
ALERT
RESET
60
100
200
kΩ
1
3
6
ALERT
0.2
V_OL
Logic low output voltage level RESET; V_(BAT) = 7 V; V_(REG25) = 1.5 V; I _(RESET) = 200 μA
GPOD; I_(GPOD) = 50 μA
LOGIC SMBC, SMBD, PFIN, PRES, SAFE, ALERT, DISP
0.4
V
0.6
V_IH
High-level input voltage
V_IL
Low-level input voltage
V_OH
Output voltage high⁽¹⁾
I_L = –0.5 mA
2.0
V_REG25–0.
5
V
0.8
V
V
V_OL
C_I
I_(SAFE)
I_lkg(SAFE)
I_lkg
ADC ⁽²⁾
Low-level output voltage
Input capacitance
SAFE source currents
SAFE leakage current
Input leakage current
PRES, PFIN, ALERT, DISP; I_L = 7 mA;
SAFE active, SAFE = V_(REG25) –0.6 V
SAFE inactive
5
–3
–0.2
0.4
V
pF
mA
0.2
µA
1
µA
Input voltage range
Conversion time
TS1, TS2, using Internal V_ref
–0.2
1
V
31.5
ms
Resolution (no missing
codes)
16
bits
Effective resolution
Integral nonlinearity
Offset error⁽⁴⁾
Offset error drift⁽⁴⁾
T_A = 25°C to 85°C
14
15
bits
±0.03
%FSR ⁽³⁾
140
250
µV
2.5
18
μV/°C
(1) RC[0:7] bus
(2) Unless otherwise specified, the specification limits are valid at all measurement speed modes.
(3) Full-scale reference
(4) Post-calibration performance and no I/O changes during conversion with SRN as the ground reference.
Copyright © 2011, Texas Instruments Incorporated
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