BQ2052_15 Datasheet, PDF (9/20 Pages) Texas Instruments – Gas Gauge IC

Not Recommended For New Designs
Preliminary bq2052
Communicating With the bq2052
The bq2052 includes a simple single-pin (HDQ plus re-
turn) serial data interface. A host processor uses the in-
terface to access various bq2052 registers. Battery char-
acteristics may be easily monitored by adding a single
contact to the battery pack. The open-drain HDQ pin on
the bq2052 should be pulled up by the host system, or
may be left floating if the serial interface is not used.
The interface uses a command-based protocol, where the
host processor sends a command byte to the bq2052.
The command directs the bq2052 to either store the next
eight bits of data received to a register specified by the
command byte or output the eight bits of data specified
by the command byte.
The communication protocol is asynchronous re-
turn-to-one. Command and data bytes consist of a
stream of eight bits that have a maximum transmission
rate of 5K bits/sec. The least-significant bit of a com-
mand or data byte is transmitted first. The protocol is
simple enough that it can be implemented by most host
processors using either polled or interrupt processing.
Data input from the bq2052 may be sampled using the
pulse-width capture timers available on some
microcontrollers.
If a communication error occurs, e.g., t_CYCB > 250µs, the
bq2052 should be sent a BREAK to reinitiate the serial
interface. A BREAK is detected when the HDQ pin is
driven to a logic-low state for a time, t_B or greater. The
HDQ pin should then be returned to its normal
ready-high logic state for a time, t_BR. The bq2052 is now
ready to receive a command from the host processor.
The return-to-one data bit frame consists of three dis-
tinct sections. The first section is used to start the
transmission by either the host or the bq2052 taking the
HDQ pin to a logic-low state for a period, t_STRH;B. The
next section is the actual data transmission, where the
data should be valid by a period, t_DSU;B, after the nega-
tive edge used to start communication. The data should
be held for a period, t_DH;DV, to allow the host or bq2052
to sample the data bit.
The final section is used to stop the transmission by re-
turning the HDQ pin to a logic-high state by at least a pe-
riod, t_SSU;B, after the negative edge used to start commu-
nication. The final logic-high state should be until a pe-
riod t_CYCH;B, to allow time to ensure that the bit trans-
mission was stopped properly. The timings for data and
break communication are given in the serial communica-
tion timing specification and illustration sections.
Communication with the bq2052 is always performed
with the least-significant bit being transmitted first.
Figure 5 shows an example of a communication se-
quence to read the bq2052 NAC register.
bq2052 Command Code and
Registers
The bq2052 status registers are listed in Table 6 and de-
scribed below.
Command Code
The bq2052 latches the command code when eight valid
command bits have been received by the bq2052. The
command code contains two fields:
I W/R bit
I Command address
The W/R bit of the command code is used to select whether
the received command is for a read or a write function.
The W/R values are:
Command Code Bits
7
65
4
3
2
1
0
W/R - -
-
-
-
-
-
Where W/R is:
0 The bq2052 outputs the requested register con-
tents specified by the address portion of com-
mand code.
1 The following eight bits should be written to the
register specified by the address portion of com-
mand code.
The lower seven-bit field of the command code contains
the address portion of the register to be accessed. At-
tempts to write to invalid addresses are ignored.
Command Code Bits
7
6
5
4
3
2
1
0
-
AD6 AD5 AD4 AD3
AD2
AD1
AD0
(LSB)
Command Word (CMDWD)
The CMDWD register (address = 00h) is used by the ex-
ternal host to control the CP pin and to reset the
bq2052.
CMDWD
Action
0x55 CP high impedence, CPIN bit in FLGS1 set
0x66 CP driven low, CPIN bit in FLGS1 cleared
0x78 bq2052 reset
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