AMC1306E05 Datasheet, PDF (9/40 Pages) Texas Instruments – Small, High-Precision, Reinforced Isolated Delta-Sigma Modulators with High CMTI

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AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25
SBAS734 – MARCH 2017
7.10 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
f_CLKIN
CLKIN clock frequency
4.5 V ≤ AVDD ≤ 5.5 V
3.0 V ≤ AVDD ≤ 5.5 V
5
21
MHz
5
20
t_CLKIN
CLKIN clock period
4.5 V ≤ AVDD ≤ 5.5 V
3.0 V ≤ AVDD ≤ 5.5 V
47.6
200
ns
50
200
t_HIGH
t_LOW
t_H
CLKIN clock high time
CLKIN clock low time
DOUT hold time after rising edge of
CLKIN
AMC1306Mx⁽¹⁾, C_LOAD = 15 pF
20
25
120 ns
20
25
120 ns
3.5
ns
t_D
Rising edge of CLKIN to DOUT valid
delay
AMC1306Mx⁽¹⁾, C_LOAD = 15 pF
15 ns
t_r
DOUT rise time
t_f
DOUT fall time
t_ISTART Interface startup time
10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V,
C_LOAD = 15 pF
10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V,
C_LOAD = 15 pF
10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V,
C_LOAD = 15 pF
10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V,
C_LOAD = 15 pF
DVDD at 2.7 V (min) to DOUT valid
with AVDD ≥ 3.0 V
0.8
3.5
ns
1.8
3.9
0.8
3.5
ns
1.8
3.9
32
32
CLKIN
cycles
t_ASTART Analog startup time
AVDD step to 3.0 V with DVDD ≥ 2.7 V,
0.1% settling
0.5
ms
(1) The output of the Manchester encoded versions of the AMC1306Ex can change with every edge of CLKIN with a typical delay of 6 ns;
see the Manchester Coding Feature section for additional details.
tCLKIN
tHIGH
CLKIN
tLOW
tH
tD
tr / tf
DOUT
Figure 1. Digital Interface Timing
AVDD
DVDD
CLKIN
DOUT
tASTART
...
Test Pattern
tISTART
Bitream not valid
(analog settling)
Figure 2. Device Startup Timing
Valid bitstream
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