ADS7882_14 Datasheet, PDF (9/30 Pages) Texas Instruments – 12-BIT, 3-MSPS LOW POWER SAR ANALOG-TO-DIGITAL CONVERTER

ADS7882
www.ti.com ........................................................................................................................................................................................... SLAS630 – DECEMBER 2008
CONVERSION ABORT
The falling edge of CS aborts the conversion while BUSY is high and CONVST is high (see Figure 4). The
device outputs FE0 (hex) to indicate a conversion abort.
BUSY
CONVST
t_d5
t_su1
CS
RD
D11−D0
1111 1110 0000
Figure 4. Conversion Abort
DATA READ
Two conditions need to be satisfied for a read operation. Data appears on the D11 through D0 pins (with D11
MSB) when both CS and RD are low. Figure 5 and Figure 6 illustrate the device read operation. The bus is
3-stated if any one of the signals is high.
CONVST
BUSY
CS
t_d2
t_(conv)
t_d11
t₁
t_w5
t_d1 + t_(acq)
RD
BYTE
D11−D0
t_d6
t_d7
t_d9
D11−4 & D3−0
D3−0
Figure 5. Read Control via CS and RD
There are two output formats available. Twelve bit data appears on the bus during a read operation while BYTE
is low. When BYTE is high, the lower byte (D3 through D0 followed by all zeroes) appears on the data bus with
D3 in the MSB. This feature is useful for interfacing with eight bit microprocessors and microcontrollers.
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