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ADS7813 Datasheet, PDF (9/25 Pages) Burr-Brown (TI) – Low-Power, Serial 16-Bit Sampling ANALOG-TO-DIGITAL CONVERTER
DESCRIPTION
ANALOG INPUT
DIGITAL OUTPUT
Full-Scale Range
Least Significant Bit (LSB)
±10V
305µV
0.5V to 4.5V
61µV
BINARY TWO’S COMPLEMENT
BINARY CODE
HEX CODE
+Full Scale –1LSB
9.999695V
4.499939V
0111 1111 1111 1111
Midscale
Midscale –1LSB
–Full Scale
0V
–305µV
–10V
2.5V
2.499939µV
0.5V
0000 0000 0000 0000
1111 1111 1111 1111
10000 0000 0000 0000
TABLE III. Ideal Input Voltage and Corresponding Digital Output for Two Common Input Ranges.
7FFF
0000
FFFF
8000
Converter Core
CONV
EXT/INT
REF
CDAC
Clock
Control Logic
Each flip-flop in the
working register is
latched as the
conversion proceeds
Working Register
DQ
W0
DQ
DQ
DQ
DQ
•••
W1
W2
W14
Update of the shift
register occurs just prior
to BUSY Rising(1)
DQ
DQ
DQ
DQ
W15
Shift Register
DQ
DQ
S0
S1
S2
S14
S15
SOUT
Delay
BUSY
DATA
DATACLK
CS
NOTE: (1) If EXT/INT is HIGH (external clock), DATACLK is HIGH, and CS is LOW during
this time, the shift register will not be updated and the conversion result will be lost.
FIGURE 3. Block Diagram of the ADS7813’s Digital Inputs and Outputs.
CONV
BUSY
t25
t6 – t25
NOTE: Update of the internal shift register occurs in the
shaded region. If EXT/INT is HIGH, then DATACLK
must be LOW or CS must be HIGH during this time.
FIGURE 4. Timing of the Shift Register Update.
ADS7813
SBAS043C
READING DATA
The ADS7813 digital output is in Binary Two’s Comple-
ment (BTC) format. Table III shows the relationship be-
tween the digital output word and the analog input voltage
under ideal conditions.
Figure 3 shows the relationship between the various digital
inputs, digital outputs, and internal logic of the ADS7813.
Figure 4 shows when the internal shift register of the
ADS7813 is updated and how this relates to a single conver-
sion cycle. Together, these two figures point out a very
important aspect of the ADS7813: the conversion result is
not available until after the conversion is complete. The
implications of this are discussed in the following sections.
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