TMS320VC5507_17 Datasheet, PDF (87/137 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.7 Memory Interface Timings
5.7.1 Asynchronous Memory Timings
Table 5−7 and Table 5−8 assume testing over recommended operating conditions (see Figure 5−6 and
Figure 5−7).
Table 5−7. Asynchronous Memory Cycle Timing Requirements
NO.
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
UNIT
MIN MAX MIN MAX
M1 tsu(DV-COH)
Setup time, read data valid before CLKOUT high†
6
5
ns
M2 th(COH-DV)
M3 tsu(ARDY-COH)
Hold time, read data valid after CLKOUT high
Setup time, ARDY valid before CLKOUT high†
0
0
ns
10
7
ns
M4 th(COH-ARDY)
Hold time, ARDY valid after CLKOUT high
0
0
ns
† _{To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold}
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
Table 5−8. Asynchronous Memory Cycle Switching Characteristics
NO.
M5 td(COH-CEV)
M6 td(COH-CEIV)
M7 td(COH-BEV)
M8 td(COH-BEIV)
M9 td(COH-AV)
M10 td(COH-AIV)
M11 td(COH-AOEV)
M12 td(COH-AOEIV)
M13 td(COH-AREV)
M14 td(COH-AREIV)
M15 td(COH-DV)
M16 td(COH-DIV)
M17 td(COH-AWEV)
M18 td(COH-AWEIV)
PARAMETER
Delay time, CLKOUT high to CEx valid
Delay time, CLKOUT high to CEx invalid
Delay time, CLKOUT high to BEx valid
Delay time, CLKOUT high to BEx invalid
Delay time, CLKOUT high to address valid
Delay time, CLKOUT high to address invalid
Delay time, CLKOUT high to AOE valid
Delay time, CLKOUT high to AOE invalid
Delay time, CLKOUT high to ARE valid
Delay time, CLKOUT high to ARE invalid
Delay time, CLKOUT high to data valid
Delay time, CLKOUT high to data invalid
Delay time, CLKOUT high to AWE valid
Delay time, CLKOUT high to AWE invalid
CVDD = 1.2 V
CVDD = 1.35 V
MIN MAX
−2
4
−2
4
4
−2
4
−2
−2
4
−2
4
−2
4
−2
4
4
−2
−2
4
−2
4
CVDD = 1.6 V
MIN MAX
−2
4
−2
4
4
−2
4
−2
−2
4
−2
4
−2
4
−2
4
4
−2
−2
4
−2
4
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
April 2004 − Revised January 2008
SPRS244J
87