TMS320VC5421PGE200 Datasheet, PDF (87/104 Pages) Texas Instruments – TMS320VC5421 Fixed-Point Digital Signal Processor

Electrical Specifications
5.14.4 McBSP as SPI Master or Slave Timing
The following timing requirements and switching characteristics tables assume testing over recommended
operating conditions and H = 0.5t_c(CO) (see Figure 5−23, Figure 5−24, Figure 5−25, and Figure 5−26).
Table 5−27. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)^†
MASTER
MIN MAX
SLAVE
UNIT
MIN MAX
tsu(BDRV-BCKXL)
th(BCKXL-BDRV)
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX low
12
2 − 12H
ns
4
6 + 12H
ns
tsu(BFXL-BCKXH) Setup time, BFSX low before BCLKX high
10
ns
tc(BCKX)
Cycle time, BCLKX
12H
32H
ns
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
Table 5−28. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)^†
PARAMETER
MASTER^‡
MIN MAX
SLAVE
UNIT
MIN
MAX
th(BCKXL-BFXL)
td(BFXL-BCKXH)
Hold time, BFSX low after BCLKX low§
Delay time, BFSX low to BCLKX high¶
T−5 T+6
ns
C−5 C+5
ns
td(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid
−3
12 6H + 4 10H + 19 ns
tdis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit from BCLKX
low
C − 6 C +10
ns
tdis(BFXH-BDXHZ)
Disable time, BDX high impedance following last data bit from BFSX
high
4H+ 4 8H + 17 ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
4H + 4 8H + 17 ns
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
‡ _{T = BCLKX period = (1 + CLKGDV) * 2H}
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
§ _{FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX}
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶ _{BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock}
(BCLKX).
BCLKX
BFSX
BDX
BDR
LSB
tsu(BFXL-BCKXH)
MSB
tc(BCKX)
th(BCKXL-BFXL)
td(BFXL-BCKXH)
Bit 0
Bit 0
tdis(BFXH-BDXHZ)
tdis(BCKXL-BDXHZ)
tsu(BDRV-BCKXL)
td(BFXL-BDXV)
td(BCKXH-BDXV)
Bit(n-1)
(n-2)
(n-3)
Bit(n-1)
th(BCKXL-BDRV)
(n-2)
(n-3)
(n-4)
(n-4)
Figure 5−23. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
December 1999 − Revised October 2008
SPRS098D
87