RM42L432 Datasheet, PDF (86/99 Pages) Texas Instruments – RM42L432 16/32-Bit RISC Flash Microcontroller

RM42L432
SPNS180 – SEPTEMBER 2012
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5.7.5 SPI Slave Mode I/O Timings
Table 5-15. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO =
input, and SPISOMI = output)^(1)(2)(3)(4)
NO.
1
2 ⁽⁶⁾
3 ⁽⁶⁾
4 ⁽⁶⁾
Parameter
t_c(SPC)S
t_w(SPCH)S
t_w(SPCL)S
t_w(SPCL)S
t_w(SPCH)S
t_{d(SPCH-SOMI)S}
Cycle time, SPICLK⁽⁵⁾
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Delay time, SPISOMI valid after SPICLK high (clock
polarity = 0)
MIN
30
14
14
14
14
MAX
256t_c(VCLK)
t_rf(SOMI) + 10
Unit
ns
ns
ns
ns
t_{d(SPCL-SOMI)S}
Delay time, SPISOMI valid after SPICLK low (clock polarity
= 1)
5 ⁽⁶⁾
t_{h(SPCH-SOMI)S}
Hold time, SPISOMI data valid after SPICLK high (clock
2
polarity =0)
t_rf(SOMI) + 10
ns
t_{h(SPCL-SOMI)S}
Hold time, SPISOMI data valid after SPICLK low (clock
2
polarity =1)
6 ⁽⁶⁾
t_{su(SIMO-SPCL)S}
Setup time, SPISIMO before SPICLK low (clock polarity =
2
ns
0)
t_{su(SIMO-SPCH)S}
Setup time, SPISIMO before SPICLK high (clock polarity =
2
1)
7 ⁽⁶⁾
t_{h(SPCL-SIMO)S}
Hold time, SPISIMO data valid after SPICLK low (clock
2
ns
polarity = 0)
t_{h(SPCH-SIMO)S}
Hold time, SPISIMO data valid after S PICLK high (clock
2
polarity = 1)
8
t_{d(SPCL-SENAH)S}
Delay time, SPIENAn high after last SPICLK low (clock
polarity = 0)
1.5t_c(VCLK)
2.5t_c(VCLK)+t_r(ENAn)
ns
t_{d(SPCH-SENAH)S}
Delay time, SPIENAn high after last SPICLK high (clock
polarity = 1)
1.5t_c(VCLK)
2.5t_c(VCLK)+_tr(ENAn)
9
t_{d(SCSL-SENAL)S}
Delay time, SPIENAn low after SPICSn low (if new data
has been written to the SPI buffer)
t_f(ENAn)
t_c(VCLK)+t_f(ENAn)+1
ns
4
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) If the SPI is in slave mode, the following must be true: t_c(SPC)S ≥ (PS + 1) t_c(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see Table 3-4.
(4) t_c(VCLK) = interface clock cycle time = 1 /f_(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: t_c(SPC)S ≥ (PS +1)t_c(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: t_c(SPC)S = 2t_c(VCLK) ≥ 40ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
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Peripheral Information and Electrical Specifications
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