TPS65930_11 Datasheet, PDF (85/117 Pages) Texas Instruments – Integrated Power Management / Audio Codec (TPS65930 Only)

TPS65930/TPS65920
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SWCS037G – MAY 2008 – REVISED APRIL 2011
CLKREQ pin. As a result, the TPS65920/TPS65930 device immediately sets CLKEN to 1 to warn the
clock provider in the system about the clock request and starts a timer (maximum of 5.2 ms using the
32.768-kHz clock). When the timer expires, the TPS65920/TPS65930 device opens a gated clock, the
timer automatically reloads the defined value, and a high-frequency output clock signal is available
through the HFCLKOUT pin. The output drive of HFCLKOUT is programmable (minimum load 10 pF,
maximum load 40 pF) and must be at 40 pF by default.
With a register setting, the mirroring of CLKEN can be enabled on CLKEN2. When this mirroring feature is
not enabled, CLKEN2 can be used as a general-purpose output controlled through I²C accesses.
CLKREQ, when enabled, has a weak pulldown resistor to support the wired-OR clock request.
Figure 11-3 shows an example of the wired-OR clock request.
PERIPH1
VIO
Device
PERIPH2
CLKREQ
VIO
PERIPHn
VIO
Figure 11-3. Example of Wired-OR Clock Request
037-043
The timer default value must be the worst case (10 ms) for the clock providers. For legacy or workaround
support, the NSLEEP1 and NSLEEP2 signals can also be used as a clock request even if it is not their
primary goal. By default, this feature is disabled and must be enabled individually by setting the register
bits associated with each signal.
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Clock Specifications
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