LM3S9DN5 Datasheet, PDF (845/1388 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S9DN5 Microcontroller
■ Set the audio format using the Justification (JST), Data Delay (DLY), SCLK polarity (SCP),
and Left-Right Polarity (LRP) bits written to the I2STXCFG and I2SRXCFG registers. The
settings are shown in the table below.
Table 16-9. Audio Formats Configuration
Audio Format
I²S
Left-Justified
Right-Justified
I2STXCFG/I2SRXCFG Register Bit
JST
DLY
SCP
LRP
0
1
0
1
0
0
0
0
1
0
0
0
16.5
■ Write 0x0140.3DF0 to both the I2STXCFG and I2SRXCFG registers to program the following
configurations:
– Set the sample size to 16 bits using the SSZ field of the I2STXCFG and I2SRXCFG
registers.
– Set the system data size to 32 bits using the SDSZ field of the I2STXCFG and I2SRXCFG
registers.
– Set the Write and Read modes using the WM and RM fields in the I2STXCFG and
I2SRXCFG registers, respectively.
8. Set up the FIFO limits for triggering interrupts (also used for µDMA)
■ Set up the transmit FIFO to trigger when it has less than four sample pairs by writing a
0x0000.0008 to the I2STXLIMIT register.
■ Set up the receive FIFO to trigger when there are more than four sample pairs by writing a
0x0000.00008 to the I2SRXLIMIT register.
9. Enable interrupts.
■ Enable the transmit FIFO interrupt by setting the FFM bit in the I2STXISM register (write
0x0000.0001).
■ Set up the receive FIFO interrupts by setting the FFM bit in the I2SRXISM register (write
0x0000.0001).
■ Enable the TX FIFO service request, the TX Error, the RX FIFO service request, and the
RX Error interrupts to be sent to the CPU by writing a 0x0000.0033 to the I2SSIM register.
10. Enable the Serial Encoder and Serial Decoders by writing a 0x0000.0003 to the I2SCFG register.
Register Map
Table 16-10 on page 846 lists the I²S registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the I²S interface base address of 0x4005.4000. Note that the I²S
module clock must be enabled before the registers can be programmed (see page 270). There must
be a delay of 3 system clocks after the I²S module clock is enabled before any I²S module registers
are accessed.
January 23, 2012
845
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