LM3S1R26 Datasheet, PDF (84/802 Pages) Texas Instruments – Stellaris® LM3S1R26 Microcontroller

The Cortex-M3 Processor
2.5.3
2.5.4
Table 2-9. Interrupts (continued)
Vector Number
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54-58
59
60-61
62
63
64-69
70
Interrupt Number (Bit
in Interrupt Registers)
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38-42
43
44-45
46
47
48-53
54
Vector Address or
Offset
0x0000.0090
0x0000.0094
0x0000.0098
0x0000.009C
0x0000.00A0
0x0000.00A4
0x0000.00A8
-
0x0000.00B0
0x0000.00B4
0x0000.00B8
0x0000.00BC
0x0000.00C0
0x0000.00C4
0x0000.00C8
0x0000.00CC
0x0000.00D0
0x0000.00D4
-
0x0000.00EC
-
0x0000.00F8
0x0000.00FC
-
0x0000.0118
Description
Timer 0B
Timer 1A
Timer 1B
Timer 2A
Timer 2B
Analog Comparator 0
Analog Comparator 1
Reserved
System Control
Flash Memory Control
GPIO Port F
GPIO Port G
GPIO Port H
UART2
SSI1
Timer 3A
Timer 3B
I²C1
Reserved
Hibernation Module
Reserved
µDMA Software
µDMA Error
Reserved
GPIO Port J
Exception Handlers
The processor handles exceptions using:
■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs.
■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault
exceptions handled by the fault handlers.
■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system
exceptions that are handled by system handlers.
Vector Table
The vector table contains the reset value of the stack pointer and the start addresses, also called
exception vectors, for all exception handlers. The vector table is constructed using the vector address
or offset shown in Table 2-8 on page 83. Figure 2-6 on page 85 shows the order of the exception
vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the
exception handler is Thumb code
84
January 21, 2012
Texas Instruments-Production Data