LM3S9L71_15 Datasheet, PDF (836/1283 Pages) Texas Instruments – Stellaris LM3S9L71 Microcontroller

Ethernet Controller
Table 17-2. Ethernet Signals (108BGA) (continued)
Pin Name
Pin Number Pin Mux / Pin Pin Type Buffer Type^a Description
Assignment
RXD1
K4
PF7 (3)
I
A8
PB7 (7)
TTL
MII receive data 1.
RXD2
M8
PF6 (3)
I
TTL
MII receive data 2.
RXD3
L8
PF5 (3)
I
TTL
MII receive data 3.
RXDV
G1
PD0 (7)
I
M5
PA5 (3)
G3
PH6 (9)
TTL
MII receive data valid.
RXER
F3
PJ0 (3)
I
M6
PA7 (3)
H12
PF1 (4)
TTL
MII receive error.
TXCK
L7
PG6 (3)
I
TTL
MII transmit clock. 25 MHz in 100BASE-TX mode.
2.5 MHz in 10BASE-T mode.
TXD0
L5
PA4 (3)
O
F10
PH5 (9)
A2
PD7 (4)
TTL
MII transmit data 0.
TXD1
L4
PA3 (3)
O
B10
PH4 (9)
A3
PD6 (4)
TTL
Ethernet MII transmit data 1.
TXD2
M4
PA2 (3)
O
D10
PH3 (9)
C6
PD5 (4)
TTL
MII transmit data 2.
TXD3
L1
PC4 (3)
O
D11
PH2 (9)
B5
PD4 (4)
TTL
Ethernet MII transmit data 3.
TXEN
M7
PG5 (3)
O
TTL
MII transmit enable.
TXER
G2
PD1 (7)
O
C10
PG7 (3)
TTL
MII transmit error.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
17.3
Functional Description
The functional description of the Ethernet Controller is discussed in the following sections.
17.3.1
MAC Operation
The following sections describe the operation of the MAC layer, including an overview of the Ethernet
frame format, the MAC layer FIFOs, Ethernet transmission and reception options, packet timestamps,
and LED indicators.
17.3.1.1
Ethernet Frame Format
Ethernet data is carried by Ethernet frames. The basic frame format is shown in Figure
17-3 on page 836.
Figure 17-3. Ethernet Frame
Preamble
7
Bytes
SFD Destination Address
Source Address
Length/
Type
1
Byte
6
Bytes
6
Bytes
2
Bytes
Data
46 - 1500
Bytes
FCS
4
Bytes
836
July 03, 2014
Texas Instruments-Production Data