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TMS320F28379S Datasheet, PDF (80/209 Pages) Texas Instruments – Microcontrollers
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TMS320F28379S, TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881B – AUGUST 2014 – REVISED OCTOBER 2015
www.ti.com
Table 5-33 shows the HALT mode timing requirements, Table 5-34 shows the switching characteristics,
and Figure 5-18 shows the timing diagram for HALT mode.
Table 5-33. HALT Mode Timing Requirements
MIN
MAX
UNIT
tw(WAKE-GPIO)
tw(WAKE-XRS)
Pulse duration, GPIO wakeup signal(1)
Pulse duration, XRS wakeup signal(1)
toscst + 2tc(OSCCLK)
toscst + 8tc(OSCCLK)
cycles
cycles
(1) For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on
circuit/layout external to the device. See Table 5-17 for more information. For applications using INTOSC1 or INTOSC2 for OSCCLK,
see Section 5.7.3.5 for toscst. Oscillator start-up time does not apply to applications using a single-ended crystal on the X1 pin, as it is
powered externally to the device.
Table 5-34. HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
td(IDLE-XCOS)
Delay time, IDLE instruction executed to XCLKOUT stop
Delay time, external wake signal end to CPU1 program
execution resume
MIN
MAX
16tc(INTOSC1)
UNIT
cycles
td(WAKE-HALT)
• Wakeup from flash
– Flash module in active state
• Wakeup from flash
– Flash module in sleep state
75tc(OSCCLK)
17500tc(OSCCLK) (1)
cycles
• Wakeup from RAM
75tc(OSCCLK)
(1) This value is based on the Flash power-up time, which is a function of the SYSCLK frequency, Flash Waitstates (RWAIT), and
FPAC1[PSLEEP]. For more information, see the "Flash and OTP Power-Down Modes and Wakeup" section of the TMS320F2837xS
Delfino Microcontrollers Technical Reference Manual (SPRUHX5). This value can be realized when SYSCLK is 200 MHz, RWAIT is 3,
and FPAC1[PSLEEP] is 0x860.
80
Specifications
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