TPS23841_16 Datasheet, PDF (8/49 Pages) Texas Instruments – HIGH-POWER, WIDE VOLTAGE RANGE, QUAD-PORT ETHERNET POWER SOURCING EQUIPMENT MANAGER

TPS23841
SLUS745A – NOVEMBER 2006 – REVISED MAY 2007
www.ti.com
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
PAP PJD
POWER AND GROUND
V48
60
5
V10
58
7
V6.3
59
6
V3.3
24
41
V2.5
54
11
AG1
57
8
AG2
DG
61
4
23
42
RG
56
9
PORT ANALOG SIGNAL
P1
7
58
P2
10
55
P3
39
26
P4
42
23
N1
6
59
N2
11
54
N3
38
27
N4
43
22
RET1
5
60
RET2
12
53
RET3
37
28
RET4
44
21
CINT1
4
61
CINT2
13
52
CINT3
36
29
CINT4
45
20
I/O
DESCRIPTION
I
48-V input to the device. This supply can have a range of 22 V to 57 V. This pin should be decoupled
with a 0.1-µF capacitor from V48 to AG1 placed as close to the device as possible.
10-V analog supply. The 10-V reference is generated internally and connects to the main internal
O analog power bus. A 0.1-µF de-coupling capacitor should terminate as close to this node and the
AG1 pin as possible. Do not use for an external supply.
O
6.3-V analog supply. A 0.1-µF de-coupling capacitor should terminate as close to this pin and the
AG1 pin as possible. Do not use for an external supply.
3.3-V logic supply. The 3.3-V supply is generated internally and connects to the internal logic power
O bus. A 0.1-µìF de-coupling capacitor should terminate as close to this node and the DG pin as
possible. This output can be used as a low current supply to external logic.
2.5-V reference supply. The V2.5 is generated internally and connects to the internal reference power
O bus. This pin should not be tied to any external supplies. A 0.1-µF de-coupling capacitor should
terminate as close to this node and the RG pin as possible. Do not use for an external supply.
Analog ground 1. This is the analog ground of the V6.3, V10 and V48 power systems. It should be
GND externally tied to the common copper 48-V return plane. This pin should carry the low side of three
de-coupling capacitors tied to V48, V10 and V6.3.
Analog ground 2. This is the analog ground which ties to the substrate and ESD structures of the
GND device. It should be externally tied to the common copper 48-V return plane. AG1 and AG2 must be
tied together directly for the best noise immunity.
GND
Digital ground. This pin connects to the internal logic ground bus. It should be externally tied to the
common copper 48-V return plane.
Reference ground. This is a precision sense of the external ground plane. The integration capacitor
GND
(CINT) and the biasing resistor (RBIAS pin) should be tied to this ground. This ground should also be
used to form a printed wiring board ground guard ring around the active node of the integration
capacitor (CINT). It should tie to common copper 48-V return plane.
I
I ^{Port Positive. 48-V load sense pin. Terminal voltage is monitored and controlled differentially with}
respect to each Port N pin Optionally, if the application warrants, this high side path can be protected
I _{with the use of a self resetting poly fuse.}
I
I
I _{Port negative. 48-V load return pin. The low side of the load is switched and protected by internal}
I ^{circuitry that will limit the current.}
I
I
I
48 V return pin
I
I
I
Integration capacitor. This capacitor is used for the ramp A/D converter signal integration. Connect A
I _{0.027- µF capacitor from this pin to RG. To minimize errors use a polycarbonate, poly-polypropylene,}
I ^{polystyrene or teflon capacitor type to prevent leakage. Other types of capacitors can be used with}
increased conversion error.
I
8
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