TLC532AI Datasheet, PDF (8/10 Pages) Texas Instruments – LinCMOSE 8-BIT ANALOG-TO-DIGITAL PERIPHERALS WITH 5 ANALOG AND 6 DUAL-PURPOSE INPUTS

TLC532AI, TLC532AM
LinCMOS™ 8-BIT ANALOG-TO-DIGITAL PERIPHERALS
WITH 5 ANALOG AND 6 DUAL-PURPOSE INPUTS
SLAS070 – D2819, NOVEMBER 1983 – REVISED SEPTEMBER 1986
electrical characteristics over recommended operating free-air temperature range, V_REF+ = V_CC,
V_REF– at ground, f_CLK = 2 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP† MAX UNIT
VOH
VOL
IIH
High-level output voltage
Low-level output voltage
High-level input current
Any digital or Clock input
Any control input
IOH = – 1.6 mA
IOL = 1.6 mA
VIH = 5.5 V
2.4
V
0.4
V
10
µA
1
Any digital or Clock input
IIL
Low-level input current
Any control input
VIL = 0
– 10
µA
–1
IOZ
Off-state (high-impdance state) output current
VO = VCC
VO = 0
II
Analog input current (see Note 3)
VI = 0 to VCC
Leakage current between selected channel
and all other analog channels
VI = 0 to VCC, Clock input at 0 V
10
µA
– 10
±500 nA
±400 nA
Digital pins 3 thru 10
Ci
Input capacitance
Any other input pin
4 30
pF
2 15
ICC + IREF+ Supply current plus reference current
VCC = VREF+ = 5.5 V,
Outputs open
1.5
3 mA
ICC
Supply current
VCC = 5.5 V
1.4
2 mA
NOTE 3: Analog input current is an average of the current flowing into a selected analog channel input during one full conversion cycle.
operating chacteristics over recommended ranges V_CC, V_REF+, and operating free-air temperature,
V_REF– at ground, f_clock = 2 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS MIN TYP† MAX UNIT
Linearity error (see Note 4)
±0.5 LSB
Zero error (see Note 5)
±0.5 LSB
Full-scale error (see Note 5)
±0.5 LSB
Total unadjusted error (see Note 6)
±0.5 LSB
Absolute accuracy error (see Note 7)
±1 LSB
tconv Conversion time (including channel acquisition time)
30
Clock
Cycles
tacq Channel acquisition time prior to starting conversion
10
Clock
Cycles
ten
Data output enable time (see Note 8)
CL = 50 pF, RL = 3 kΩ
tdis Data output disable time
CL = 50 pF, RL = 3 kΩ
10
tr(bus) Data output rise time
High-impedance to high level
Low-to-high level
CL = 50 pF, RL = 3 kΩ
250 ns
ns
150
ns
300
tf(bus) Data output fall time
High-impedance to low level
High-to-low level
CL = 50 pF, RL = 3 kΩ
150
ns
300
† _{Typical values are at VCC = 5 V, TA = 25°C.}
NOTES: 4. Linearity error is the deviation from the best straight line through the A/D transfer characteristics.
5. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference between
11111111 and the converted output for full-scale input voltage.
6. Total unadjusted error is the sum of liinearity, zero, and full-scale errors.
7. Absolute accuracy error is the maximum difference between an analog value and the nominal midstep value within any step. This
includes all errors including inherent quantization error, which is the ±0.5 LSB uncertainty caused by the A/D converters’ finite
resolution.
8. If chip-select setup time, tsu(CS), is less than 0.14 µs, the effective data output enable time, ten, may extend such that tsu(CS) + ten is
equal to a maximum of 0.475 µs.
8
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