TLC372-EP Datasheet, PDF (8/17 Pages) Texas Instruments – LinCMOS™ DUAL DIFFERENTIAL COMPARATORS

TLC372-EP
LinCMOS™ DUAL DIFFERENTIAL COMPARATORS
SGLS385 – MARCH 2007
www.ti.com
PRINCIPLES OF OPERATION (continued)
Positive ESD Transients
Initial positive charged energy is shunted through Q1 to V_SS. Q1 turns on when the voltage at the input rises
above the voltage on the V_DD pin by a value equal to the V_EB of Q1. The base current increases through R2 with
input current as Q1 saturates. The base current through R2 forces the voltage at the drain and gate of Q2 to
exceed its threshold level (V_T ~ 22 V to 26 V) and turn Q2 on. The shunted input current through Q1 to V_SS is
now shunted through the n-channel enhancement-type MOSFET Q2 to V_SS. If the voltage on the input pin
continues to rise, the breakdown voltage of the zener diode D3 is exceeded, and all remaining energy is
dissipated in R1 and D3. The breakdown voltage of D3 is designed to be 24 V to 27 V, which is well below the
gate oxide voltage of the circuit to be protected.
Negative ESD Transients
The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1 and
D2 as D2 becomes forward biased. The voltage seen by the protected circuit is –0.3 V to –1 V (the forward
voltage of D1 and D2).
Circuit-Design Considerations
LinCMOS products are being used in actual circuit environments that have input voltages that exceed the
recommended common-mode input voltage range and activate the input protection circuit. Even under normal
operation, these conditions occur during circuit power up or power down, and in many cases, when the device is
being used for a signal conditioning function. The input voltages can exceed V_ICR and not damage the device
only if the inputs are current limited. The recommended current limit shown on most product data sheets is ± 5
mA. Figure 5 and Figure 6 show typical characteristics for input voltage versus input current.
Normal operation and correct output state can be expected even when the input voltage exceeds the positive
supply voltage. Again, the input current should be externally limited even though internal positive current limiting
is achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limits the current
to approximately 5-mA collector current by design. When saturated, Q1 base current increases with input
current. This base current is forced into the V_DD pin and into the device I_DD or the V_DD supply through R2
producing the current limiting effects shown in Figure 5. This internal limiting lasts only as long as the input
voltage is below the V_T of Q2.
When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage
states may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can be
severely affected. External current limiting must be used since this current is directly shunted by D1 and D2 and
no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp is
required (see Figure 7).
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