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SN74GTLPH3245 Datasheet, PDF (8/19 Pages) Texas Instruments – 32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SN74GTLPH3245
32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES291D – OCTOBER 1999 – REVISED JUNE 2005
Recommended Operating Conditions(1)(2)(3)(4)
www.ti.com
VCC
BIAS VCC
VTT
Supply voltage
Termination voltage
VREF
Reference voltage
VI
Input voltage
VIH
High-level input voltage
VIL
IIK
IOH
IOL
∆t/∆v
∆t/∆VCC
TA
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
Operating free-air temperature
GTL
GTLP
GTL
GTLP
B port
Except B port
B port
ERC
Except B port and ERC
B port
ERC
Except B port and ERC
A port
A port
B port
Outputs enabled
MIN NOM
3.15 3.3
1.14 1.2
1.35 1.5
0.74 0.8
0.87
1
VCC
VREF + 0.05
VCC – 0.6 VCC
2
GND
20
–40
MAX
3.45
1.26
1.65
0.87
1.1
VTT
5.5
5.5
VREF – 0.05
0.6
0.8
–18
–24
24
100
10
85
UNIT
V
V
V
V
V
V
mA
mA
mA
ns/V
µs/V
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V
last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs can be
connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is
acceptable, but generally, GND is connected first.
(3) VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
(4) VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction and is
activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to minimize current
drain.
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