PCA9515A_15 Datasheet, PDF (8/24 Pages) Texas Instruments – SMBus Repeater

PCA9515A
SCPS150D – DECEMBER 2005 – REVISED JUNE 2014
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9 Application and Implementation
9.1 Typical Application
A typical application is shown in Figure 3. In this example, the system master is running on a 3.3-V bus, while the
slave is connected to a 5-V bus. Both buses run at 100 kHz, unless the slave bus is isolated, and then the
master bus can run at 400 kHz. Master devices can be placed on either bus.
3.3 V
5V
SDA
SDA0
SDA1
SDA
SCL
I²C BUS MASTER
400 kHz
SCL0
SCL1
PCA9515A
EN
SCL
I²C BUS SLAVE
100 kHz
BUS 0
BUS 1
Figure 3. Typical Application
9.1.1 Design Requirements
The PCA9515A is 5.5-V tolerant, so it does not require any additional circuitry to translate between the different
bus voltages.
When one side of the PCA9515A is pulled low by a device on the I²C bus, a CMOS hysteresis-type input detects
the falling edge and causes an internal driver on the other side to turn on, thus causing the other side also to go
low. The side driven low by the PCA9515A typically is at V_OL = 0.5 V.
9.1.2 Detailed Design Procedure
Figure 4 and Figure 5 show the waveforms that are seen in a typical application. If the bus master in Figure 3
writes to the slave through the PCA9515A, Bus 0 has the waveform shown in Figure 4. This looks like a normal
I²C transmission until the falling edge of the eighth clock pulse. At that point, the master releases the data line
(SDA) while the slave pulls it low through the PCA9515A. Because the V_OL of the PCA9515A typically is around
0.5 V, a step in the SDA is seen. After the master has transmitted the ninth clock pulse, the slave releases the
data line.
9th Clock Pulse
SCL
SDA
V_OL of Master V_OL of PCA9515A
Figure 4. Bus 0 Waveforms
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