OPA124 Datasheet, PDF (8/13 Pages) Burr-Brown (TI) – Low Noise Precision Difet OPERATIONAL AMPLIFIER

APPLICATIONS INFORMATION
OFFSET VOLTAGE ADJUSTMENT
The OPA124 offset voltage is laser-trimmed and will require
no further trim for most applications. In order to reduce
layout leakage errors, the offset adjust capability has been
removed from the SOIC versions (OPA124UA and
OPA124U). The PDIP versions (OPA124PB, OPA124PA,
and OPA124P) do have pins available for offset adjustment.
As with most amplifiers, externally trimming the remaining
offset can change drift performance by about 0.3µV/°C for
each 100µV of adjusted offset. The correct circuit configu-
ration for offset adjust for the PDIP packages is shown in
Figure 1.
INPUT PROTECTION
Conventional monolithic FET operational amplifiers require
external current-limiting resistors to protect their inputs
against destructive currents that can flow when input FET
gate-to-substrate isolation diodes are forward-biased. Most
BIFET amplifiers can be destroyed by the loss of –V_CC.
Unlike BIFET amplifiers, the Difet OPA124 requires input
current limiting resistors only if its input voltage is greater
than 6V more negative than –V_CC. A 10kΩ series resistor
will limit input current to a safe level with up to ±15V input
levels, even if both supply voltages are lost (Figure 2).
Static damage can cause subtle changes in amplifier input
characteristics without necessarily destroying the device. In
precision operational amplifiers (both bipolar and FET types),
this may cause a noticeable degradation of offset voltage and
drift. Static protection is recommended when handling any
precision IC operational amplifier.
GUARDING AND SHIELDING
As in any situation where high impedances are involved,
careful shielding is required to reduce “hum” pickup in input
leads. If large feedback resistors are used, they should also
be shielded along with the external input circuitry.
Leakage currents across printed circuit boards can easily
exceed the bias current of the OPA124. To avoid leakage
problems, the OPA124 should be soldered directly into a
printed circuit board. Utmost care must be used in planning
the board layout. A “guard” pattern should completely
surround the high impedance input leads and should be
connected to a low impedance point which is at the signal
input potential.
The amplifier substrate should be connected to any input
shield or guard via pin 8 minimizing both leakage and noise
pickup (see Figure 3).
If guarding is not required, pin 8 should be connected to
ground.
+V_CC
7
2
OPA124P
3
5
4
–V_CC
NOTE: No trim on SOIC.
6
1
10kΩ to 1MΩ trim potentiometer.
(100kΩ recommended).
±10mV typical trim range.
FIGURE 1. Offset Voltage Trim for PDIP packages.
2
I_IN
1
V
0
Maximum Safe Current
–1
Maximum Safe Current
–2
–15
–10
–5
0
5
Input Voltage (V)
10
15
FIGURE 2. Input Current vs Input Voltage with ±V_CC Pins
Grounded.
Non-Inverting
Buffer
2
8
6 ^Out
OPA124
2
8
6 ^Out
OPA124
In
3
In
3
Inverting
Bottom View
In
2
8
1
6 ^Out
OPA124
7
3
8
6
5
4
Board layout for PDIP input guarding: guard top and bottom of board.
FIGURE 3. Connection of Input Guard.
®
OPA124
8