ISO721_1007 Datasheet, PDF (8/29 Pages) Texas Instruments – 3.3-V / 5-V HIGH-SPEED DIGITAL ISOLATORS

ISO721, ISO721M
ISO722, ISO722M
SLLS629J – JANUARY 2006 – REVISED JULY 2010
ELECTRICAL CHARACTERISTICS: V_CC1 and V_CC2 at 3.3-V⁽¹⁾ OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
I_CC1 V_CC1 supply current
Quiescent
25 Mbps
V_I = V_CC or 0 V, no load
I_CC2 V_CC2 supply current
ISO722/722M
Sleep Mode
Quiescent
V_I = V_CC or 0 V,
No load
EN at V_CC
EN at 0 V or
ISO721/721M
25 Mbps
V_OH High-level output voltage
V_OL Low-level output voltage
V_I(HYS) Input voltage hysteresis
I_IH
High-level input current
I_IL
Low-level input current
I_OZ
High-impedance output
current
ISO722, ISO722M
V_I = V_CC or 0 V, no load
I_OH = –4 mA, See Figure 1
I_OH = –20 mA, See Figure 1
I_OL = 4 mA, See Figure 1
I_OL = 20 mA, See Figure 1
EN, IN at 2 V
EN, IN at 0.8 V
EN, IN at V_CC
V_CC – 0.4
V_CC – 0.1
–10
C_I
Input capacitance to ground
IN at V_CC, V_I = 0.4 sin (4E6pt)
CMTI Common-mode transient immunity
V_I = V_CC or 0 V, See Figure 5
25
(1) For the 3.3-V operation, V_CC1 and V_CC2 are specified from 3 V to 3.6 V.
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TYP MAX UNIT
0.3 0.5
mA
1
2
150 mA
4 6.5
mA
5 7.5
3
V
3.3
0.2 0.4
V
0 0.1
150
mV
10 mA
mA
1 mA
1
pF
40
kV/ms
SWITCHING CHARACTERISTICS: V_CC1 and V_CC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
t_PLH
t_PHL
t_sk(p)
t_PLH
t_PHL
t_sk(p)
t_sk(pp) ⁽¹⁾
t_r
t_f
t_pHZ
t_pZH
t_pLZ
t_pZL
Propagation delay, low-to-high-level output
Propagation delay , high-to-low-level output
Pulse skew |t_PHL – t_PLH|
Propagation delay, low-to-high-level output
Propagation delay, high-to-low-level output
Pulse skew |t_PHL – t_PLH|
Part-to-part skew
Output signal rise time
Output signal fall time
Sleep-mode propagation delay,
high-level-to-high-mpedance output
Sleep-mode propagation delay,
high-impedance-to-high-level output
Sleep-mode propagation delay,
low-level-to-high-impedance output
Sleep-mode propagation delay,
high-impedance-to-low-level output
ISO72x
ISO72xM
EN at 0 V,
See Figure 1
EN at 0 V,
See Figure 1
See Figure 2
ISO722
ISO722M
See Figure 3
t_fs
t_jit(PP)
Failsafe output delay time from input power loss
See Figure 4
Peak-to-peak eye-pattern jitter
ISO72x
100-Mbps NRZ data input, See Figure 6
100-Mbps unrestricted bit run length data
input, See Figure 6
150-Mbps NRZ data input, See Figure 6
ISO72xM _{150-Mbps unrestricted bit run length data}
input, See Figure 6
MIN TYP MAX UNIT
17
20
34 ns
17
20
34 ns
0.5
3 ns
10
12
25 ns
10
12
25 ns
0.5
1 ns
0
5 ns
2
ns
2
7
13
25 ns
5
6
8 µs
7
13
25 ns
5
6
8 ms
3
ms
2
3
ns
1
2
(1) t_sk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
8
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