DS90LT012A_16 Datasheet, PDF (8/18 Pages) Texas Instruments – 3V LVDS Single CMOS Differential Line Receiver

DS90LT012A, DS90LV012A
SNLS141D – AUGUST 2002 – REVISED APRIL 2013
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Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.
Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode
rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid
discontinuities in differential impedance. Minor violations at connection points are allowable.
TERMINATION
DS90LV012A:
Use a termination resistor which best matches the differential impedance or your transmission line. The resistor
should be between 90Ω and 130Ω. Remember that the current mode outputs need the termination resistor to
generate the differential voltage. LVDS will not work without resistor termination. Typically, connecting a single
resistor across the pair at the receiver end will suffice.
Surface mount 1% - 2% resistors are the best. PCB stubs, component lead, and the distance from the
termination to the receiver inputs should be minimized. The distance between the termination resistor and the
receiver should be < 10mm (12mm MAX).
DS90LT012A:
The DS90LT012A integrates the terminating resistor for point-to-point applications. The resistor value will be
between 90Ω and 133Ω.
THRESHOLD
The LVDS Standard (ANSI/TIA/EIA-644-A) specifies a maximum threshold of ±100mV for the LVDS receiver.
The DS90LV012A and DS90LT012A support an enhanced threshold region of −100mV to 0V. This is useful for
fail-safe biasing. The threshold region is shown in the Voltage Transfer Curve (VTC) in Figure 9. The typical
DS90LV012A or DS90LT012A LVDS receiver switches at about −30mV. Note that with V_ID = 0V, the output will
be in a HIGH state. With an external fail-safe bias of +25mV applied, the typical differential noise margin is now
the difference from the switch point to the bias point. In the example below, this would be 55mV of Differential
Noise Margin (+25mV − (−30mV)). With the enhanced threshold region of −100mV to 0V, this small external fail-
safe biasing of +25mV (with respect to 0V) gives a DNM of a comfortable 55mV. With the standard threshold
region of ±100mV, the external fail-safe biasing would need to be +25mV with respect to +100mV or +125mV,
giving a DNM of 155mV which is stronger fail-safe biasing than is necessary for the DS90LV012A or
DS90LT012A. If more DNM is required, then a stronger fail-safe bias point can be set by changing resistor
values.
Figure 9. VTC of the DS90LV012A and DS90LT012A LVDS Receivers
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