DRV8800_12 Datasheet, PDF (8/27 Pages) Texas Instruments – DMOS FULL-BRIDGE MOTOR DRIVERS

DRV8800
DRV8801
SLVS855F – JULY 2008 – REVISED JANUARY 2012
www.ti.com
ABSOLUTE MAXIMUM RATINGS⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
VBB
Load supply voltage⁽²⁾
MIN
MAX UNIT
40
V
Output current
2.8
A
V_Sense
Sense voltage
VBB to OUTx
±500 mV
36
V
VDD
OUTx to SENSE
Logic input voltage⁽²⁾
36
V
–0.3
7
V
ESD rating
Human-Body Model (HBM)
Charged-Device Model (CDM)
±2
kV
500
V
Continuous total power dissipation
See Dissipation Ratings Table
T_A
Operating free-air temperature range
T_J
Maximum junction temperature
T_stg
Storage temperature range
–40
85
°C
190
°C
–40
125
°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
THERMAL INFORMATION
DRV8800/01 DRV8800/01
THERMAL METRIC
RTY
PWP
UNITS
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
Junction-to-ambient thermal resistance⁽¹⁾
Junction-to-case (top) thermal resistance⁽²⁾
Junction-to-board thermal resistance⁽³⁾
Junction-to-top characterization parameter⁽⁴⁾
Junction-to-board characterization parameter⁽⁵⁾
Junction-to-case (bottom) thermal resistance⁽⁶⁾
16 PINS
38.1
36.7
16.1
0.3
16.2
4.1
16 PINS
43.9
30.8
25.3
1.1
25
5.6
°C/W
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
V_IN
Input voltage, VBB
T_A
Operating free-air temperature
MIN NOM
8
32
–40
MAX
38
85
UNIT
V
°C
8
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