ADS7890_15 Datasheet, PDF (8/29 Pages) Texas Instruments – 14-BIT, 1.25-MSPS LOW POWER SAR ANALOG-TO-DIGITAL CONVERTER

ADS7890
SLAS409 − DECEMBER 2003
1
2
3
SCLK
CS
SDO
th2
tsu3
tw5
td3
td2
MSB
BUSY
8
9
t(cyc)
twH
14 15 16
twL
LSB
td4
t(acq), SAMPLE
Power Up
th4
td5
tw2
t(conv)
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th3
Figure 1. Device Operation With SPI Interface (FS Held High)
DEVICE OPERATION WITH DSP INTERFACE (See Figure 2)
Device operation is controlled with CS, SCLK, and FS. The frame starts with the rising edge of FS with CS
already low. The MSB is latched out first on the SDO pin. The clock cycle, with the first falling edge after the
falling edge of FS is counted as first clock. Subsequent data bits are latched out on the SDO pin with every rising
edge of further clocks (until the 14th rising edge of SCLK). The device has a built-in NAP mode. The device
enters the NAP state with an end of conversion and continues to be in this state until the 8th SCLK rising edge.
The sampling switch is closed on the 9th rising edge and the device samples the analog input [+IN− (−IN)] and
enters the conversion phase on the 16th SCLK falling edge.
CS can be pulled high at any time after this. The BUSY signal goes high to indicate the conversion is in progress
and continues to be high until the end of conversion. A new frame can be started with the end of conversion.
1
2
3
SCLK
th1
tsu2
CS
tsu1
FS
SDO
tw1
td1
td2
MSB
BUSY
8
9
t(cyc)
twH
14 15 16
twL
LSB
td4
t(acq), SAMPLE
Power Up
th4
td5
th3
tw2
t(conv)
Figure 2. Device Operation With DSP Interface
POWERDOWN/RESET
A low level on the PWD/RST pin puts the device in the powerdown phase. This is an asynchronous signal. As
shown in Figure 4, the device is in the reset phase for the first t_w3 period after the falling edge of PWD/RST.
SDO goes to three-state for a period of t_d7 after the falling edge of PWD/RST. The device powers down if the
PWD/RST pin continues to be low for a time period of more than t_w4. Data is not valid for the first four
conversions after powerup (see Figure 3) or the end of reset (see Figure 4). The device is initialized during the
first four conversions.
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