ADS7835_14 Datasheet, PDF (8/21 Pages) Texas Instruments – 12-Bit, High-Speed, Low Power Sampling ANALOG-TO-DIGITAL CONVERTER

EXTERNAL REFERENCE
The internal reference is connected to the V_REF pin and to the
internal buffer via a 10kΩ series resistor. Thus, the reference
voltage can easily be overdriven by an external reference
voltage. The voltage range for the external voltage is 2.3V
to 2.9V, corresponding to an analog input range of 2.3V to
2.9V in both cases.
While the external reference will not source significant
current into the V_REF pin, it does have to drive the 10kΩ
series resistor that is terminated into the 2.5V internal
reference (the exact value of the resistor will vary up to
±30% from part to part). In addition, the V_REF pin should
still be bypassed to ground with at least a 0.1µF ceramic
capacitor (placed as close to the ADS7835 as possible). The
reference will have to be stable with this capacitive load.
Depending on the particular reference and A/D conversion
speed, additional bypass capacitance may be required, such
as the 2.2µF tantalum capacitor shown in Figure 1.
Reasons for choosing an external reference over the internal
reference vary, but there are two main reasons. One is to
achieve a given input range. The other is to provide greater
stability over temperature. (The internal reference is typi-
cally 20ppm/°C which translates into a full-scale drift of
roughly one output code for every 12°C. This does not take
into account other sources of full-scale drift.) If greater
stability over temperature is needed, then an external refer-
ence with lower temperature drift will be required.
DIGITAL INTERFACE
Figure 2 shows the serial data timing and Figure 3 shows the
basic conversion timing for the ADS7835. The specific
timing numbers are listed in Table I. There are several
important items in Figure 3 which give the converter addi-
tional capabilities over typical 8-pin converters. First, the
transition from sample mode to hold mode is synchronous to
the falling edge of CONV and is not dependent on CLK.
Second, the CLK input is not required to be continuous
during the sample mode. After the conversion is complete,
the CLK may be kept LOW or HIGH.
The asynchronous nature of CONV to CLK raises some
interesting possibilities, but also some design consider-
ations. Figure 3 shows that CONV has timing restraints in
relation to CLK (t_CKCH and t_CKCS). However, if these times
are violated (which could happen if CONV is completely
asynchronous to CLK), the converter will perform a conver-
sion correctly, but the exact timing of the conversion is
indeterminate. Since the setup and hold time between CONV
and CLK has been violated in this example, the start of
conversion could vary by one clock cycle. (Note that the
start of conversion can be detected by using a pull-up
resistor on DATA. When DATA drops out of high imped-
ance and goes LOW, the conversion has started and that
SYMBOL
DESCRIPTION
MIN TYP MAX UNITS
t_ACQ
t_CONV
t_CKP
t_CKL
t_CKH
t_CKDH
Acquisition Time
350
ns
Conversion Time
1.625
µs
Clock Period
125
5000 ns
Clock LOW
50
ns
Clock HIGH
50
ns
Clock Falling to Current Data
5
15
ns
Bit No Longer Valid
t_CKDS
Clock Falling to Next Data Valid
30 50
ns
t_CVL
CONV LOW
40
ns
t_CVH
CONV HIGH
40
ns
t_CKCH
CONV Hold after Clock Falls⁽¹⁾
10
ns
t_CKCS
CONV Setup to Clock Falling⁽¹⁾ 10
ns
t_CKDE
Clock Falling to DATA Enabled
20 50
ns
t_CKDD
Clock Falling to DATA
High Impedance
70 100
ns
t_CKSP
Clock Falling to Sample Mode
5
ns
t_CKPD Clock Falling to Power-Down Mode
50
ns
t_CVHD
CONV Falling to Hold Mode
(Aperture Delay)
5
ns
t_CVSP
t_CVPU
t_CVDD
CONV Rising to Sample Mode
CONV Rising to Full Power-up
CONV Changing State to DATA
High Impedance
5
ns
50
ns
70 100
ns
t_CVPD
CONV Changing State to
Power-Down Mode
50
ns
t_DRP
CONV Falling to Start of CLK
(for hold droop < 0.1 LSB)
5
µs
Note: (1) This timing is not required under some situations. See text for more information.
TABLE I. Timing Specifications (T_A = –40°C to +85°C,
C_LOAD = 30pF).
CLK
DATA
t_CKH
t_CKP
t_CKL
t_CKDS
t_CKDH
FIGURE 2. Serial Data and Clock Timing.
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ADS7835
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