ADCS7476_14 Datasheet, PDF (8/30 Pages) Texas Instruments – ADCS7478 1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & WSON

ADCS7476, ADCS7477, ADCS7478
SNAS192F – APRIL 2003 – REVISED MARCH 2013
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ADCS7476/ADCS7477/ADCS7478 Specifications⁽¹⁾
ADCS7478 Converter Electrical Characteristics (continued)
The following specifications apply for V_DD = +2.7V to 5.25V, f_SCLK = 20 MHz, f_SAMPLE = 1 MSPS unless otherwise noted.
Boldface limits apply for T_A = −40°C to +85°C: all other limits T_A = 25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Typical Limits
Units
V_OH
V_OL
I_OL
C_OUT
Output High Voltage
Output Low Voltage
TRI-STATE Leakage Current
TRI-STATE Output Capacitance
Output Coding
I_SOURCE = 200 µA,
V_DD = +2.7V to +5.25V
I_SINK = 200 µA
V_DD −0.2
V (min)
0.4
V (max)
±10
µA (max)
2
4
pF (max)
Straight (Natural) Binary
AC ELECTRICAL CHARACTERISTICS
f_SCLK
DC
Clock Frequency
SCLK Duty Cycle
20
MHz (max)
40
% (min)
60
% (max)
t_TH
f_RATE
t_AD
t_AJ
Track/Hold Acquisition Time
Throughput Rate
Aperture Delay
Aperture Jitter
See Applications Information
400
ns (max)
1
MSPS (min)
3
ns
30
ps
Figure 2. Timing Test Circuit
Timing Test Circuit ADCS7476/ADCS7477/ADCS7478 Timing Specifications
The following specifications apply for V_DD = +2.7V to 5.25V, f_SCLK = 20 MHz, Boldface limits apply for T_A = −40°C to +85°C:
all other limits T_A = 25°C, unless otherwise noted. ⁽¹⁾
Symbol
Parameter
Conditions
Typical
Limits
Units
t_CONVERT
t_QUIET
t₁
t₂
t₃
(2)
Minimum CS Pulse Width
CS to SCLK Setup Time
Delay from CS Until SDATA TRI-STATE
Disabled ⁽³⁾
16 x t_SCLK
50
10
10
20
ns (min)
ns (min)
ns (min)
ns (max)
t₄
Data Access Time after SCLK Falling
Edge ⁽⁴⁾
V_DD = +2.7 to +3.6
V_DD = +4.75 to +5.25
t₅
SCLK Low Pulse Width
t₆
SCLK High Pulse Width
t₇
SCLK to Data Valid Hold Time
V_DD = +2.7 to +3.6
V_DD = +4.75 to +5.25
40
20
0.4 x
t_SCLK
0.4 x
t_SCLK
7
5
ns (max)
ns (max)
ns (min)
ns (min)
ns (min)
ns (min)
(1) All input signals are specified as t_r = t_f = 5 ns (10% to 90% V_DD) and timed from 1.6V.
(2) Minimum Quiet Time Required Between Bus Relinquish and Start of Next Conversion
(3) Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V.
(4) Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V or 2.0V.
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