LM3S1C58 Datasheet, PDF (750/846 Pages) Texas Instruments – Stellaris® LM3S1C58 Microcontroller

Signal Tables
OBSOLETE: TI has discontinued production of this device.
Table 17-2. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
PG7
I/O
TTL
GPIO port G bit 7.
36
CCP5
I/O
TTL
Capture/Compare/PWM 5.
37
PG6
I/O
TTL
GPIO port G bit 6.
VDDC
38
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.3 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to the LDO pin and an external capacitor as
specified in Table 19-6 on page 797 .
39
GND
-
Power Ground reference for logic and I/O pins.
PG5
I/O
TTL
GPIO port G bit 5.
40
CCP5
I/O
TTL
Capture/Compare/PWM 5.
PG4
I/O
TTL
GPIO port G bit 4.
41
CCP3
I/O
TTL
Capture/Compare/PWM 3.
PF7
I/O
TTL
GPIO port F bit 7.
42
CCP4
I/O
TTL
Capture/Compare/PWM 4.
PF6
I/O
TTL
GPIO port F bit 6.
43
CCP1
I/O
TTL
Capture/Compare/PWM 1.
44
VDD
-
Power Positive supply for I/O and some logic.
45
GND
-
Power Ground reference for logic and I/O pins.
PF5
I/O
TTL
GPIO port F bit 5.
46
CCP2
I/O
TTL
Capture/Compare/PWM 2.
SSI1Tx
O
TTL
SSI module 1 transmit
PF0
I/O
TTL
GPIO port F bit 0.
47
U1DSR
I
TTL
UART module 1 Data Set Ready modem output control line.
48
OSC0
I
Analog Main oscillator crystal input or an external clock reference input.
49
OSC1
O
Analog Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
50
WAKE
I
TTL
An external input that brings the processor out of Hibernate mode
when asserted.
51
HIB
O
OD
An output that indicates the processor is in Hibernate mode.
XOSC0
52
I
Analog Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a 4.194304-MHz crystal or
a 32.768-kHz oscillator for the Hibernation module RTC. See the
CLKSEL bit in the HIBCTL register.
53
XOSC1
O
Analog Hibernation module oscillator crystal output. Leave unconnected
when using a single-ended clock source.
54
GND
-
Power Ground reference for logic and I/O pins.
VBAT
55
-
Power Power source for the Hibernation module. It is normally connected
to the positive terminal of a battery and serves as the battery
backup/Hibernation module power-source supply.
56
VDD
-
Power Positive supply for I/O and some logic.
57
GND
-
Power Ground reference for logic and I/O pins.
PF4
I/O
TTL
GPIO port F bit 4.
58
CCP0
I/O
TTL
Capture/Compare/PWM 0.
SSI1Rx
I
TTL
SSI module 1 receive
750
July 24, 2012
Texas Instruments-Production Data