TWL6030 Datasheet, PDF (75/97 Pages) Texas Instruments – Fully Integrated Power Management with Switch Mode Charger

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VBUS
voltage
VADP_PRB
T_ADP_RISE
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
TA_ADP_PRB or TB_ADP_PRB
VADP_SNS
VADP_DSCHRG
T_ADP_SINK
Figure 18. ADP Timing Diagram
Time
SWCS045-017
ADP_MODE[1:0]
00
01
10
OPERATION
ADP digital module is disabled.
ADP digital module is enabled.
ADP probing mode as an A-device is enabled.
During ADP sensing mode, the VADP_SNS comparator is used. The digital module monitors the comparator
output to ensure that it toggles and the time duration between the rising edge of the comparator output signal is
shorter than T_ADP_SNS. If there is no new rising edge within the T_ADP_SNS period, the module generates
an ADP interrupt.
Figure 19 shows the ADP sensing timing diagram.
T_ADP_SNS
32.768-kHz crystal clock
ADP interrupt
ADP_MODE[1:0] 00
01
Comp (VADP_SNS)
Figure 19. ADP Sensing Timing Diagram
SWCS045-018
During ADP probing, the VADP_PRB comparator is used. The time interval measurement counter is reset, the
comparator is enabled and the VBUS_IADP_SINK current sink is turned on for T_ADP_SINK. The T_ADP_SINK
time is long enough to discharge the VBUS voltage below VADP_DSCHG (guaranteed by design). After that, the
current sink is turned off, the current source VBUS_IADP_SRC is turned on, and the time interval measurement
counter starts to count 32.768-kHz crystal clock cycles. When the VBUS voltage reaches VADP_PRB or the
counter value reaches 255 cycles, the current source is turned off, the time interval measurement counter is
stopped, and the comparator is disabled. If the measured time interval value is lower than T_ADP_LOW[7:0] or
higher than T_ADP_HIGH[7:0], an interrupt is generated. Software sets the limit values so that the operation
fulfills requirements of the OTG 2.0 specification. Figure 20 shows the ADP probing timing diagram.
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