SM320VC5507-EP_14 Datasheet, PDF (74/109 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

SM320VC5507-EP
SPRS613 – SEPTEMBER 2009
CLKMEM
CEx†
BEx ^‡
EMIF.A[13:0]
D[15:0]
SDA10
WRITE
WRITE
WRITE
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M22
M24
BE1
M26
CA1
M30
D1
M34
M25
BE2
M27
CA2
M31
D2
M23
BE3
CA3
D3
M35
SDRAS
M28
M29
SDCAS
M32
M33
SDWE
† _{The chip enable that becomes active depends on the address being accessed.}
‡ _{All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals r emain}
active until the next access that is not an SDRAM read occurs.
Figure 5-9. Three SDRAM WRT Commands
74
Electrical Specifications
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