DP83840AVCE Datasheet, PDF (74/91 Pages) Texas Instruments – 10/100 Mb/s Ethernet Physical Layer

8.0 Electrical Specifications
8.3 CLOCK TIMING
8.3.1 Clock Reference and Clock Generation Timing
Parameter
Description
Notes
T1
OSCIN to CLK25M Delay OSCIN = 50 MHz
T2
CLK25M Rise Time
10% to 90%
Min
Typ
Max
0
30
40
5
T3
CLK25M Fall Time
90% to 10%
5
T4
OSCIN to TX_CLK Delay 10 Mb/s Operation (MII
10
Nibble Mode)
T4a OSCIN to TX_CLK Delay 10 Mb/s Operation (MII
10
Serial Mode)
T5
REFIN to TX_CLK Delay 100 Mb/s Operation
-3.0
+3.0
T6
TX_CLK Duty Cycle
10 Mb/s Nibble (2.5 MHz),
35
65
10 Mb/s Serial (10 MHz)
100 Mb/s Nibble (25 MHz)
lete ^OSCIN
T1
T1
CLK25M
o _T2
T3
s _REFIN
bT5
T4
T6
O^TX_CLK
Units
ns
ns
ns
ns
ns
ns
%
Version A
73