LM4F111H5QR Datasheet, PDF (738/1115 Pages) Texas Instruments – Microcontroller

Analog-to-Digital Converter (ADC)
12.3.2.6
Module Clocking
The module is clocked by a 16-MHz clock which can be sourced by a divided version of the PLL
output, the PIOSC or an external source connected to MOSC (with the PLL in bypass mode). When
the PLL is operating, the ADC clock is derived from the PLL ÷ 25 by default. However, the PIOSC
can be used for the module clock using the ADC Clock Configuration (ADCCC) register. When
the PLL is bypassed, the module clock source clock attached to the MOSC must be 16 MHz unless
the PIOSC is used for the clock source. The ADC module can continue to operate in Deep-Sleep
mode if the PIOSC is the ADC module clock source.
12.3.3
Hardware Sample Averaging Circuit
Higher precision results can be generated using the hardware averaging circuit, however, the
improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged
to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the
number of samples in the averaging calculation. For example, if the averaging circuit is configured
to average 16 samples, the throughput is decreased by a factor of 16.
By default the averaging circuit is off, and all data from the converter passes through to the sequencer
FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC)
register (see page 774). A single averaging circuit has been implemented, thus all input channels
receive the same amount of averaging whether they are single-ended or differential.
Figure 12-6 shows an example in which the ADCSAC register is set to 0x2 for 4x hardware
oversampling and the IE1 bit is set for the sample sequence, resulting in an interrupt after the
second averaged value is stored in the FIFO.
Figure 12-6. Sample Averaging Example
A+B+C+D
4
A+B+C+D
4
INT
12.3.4
Analog-to-Digital Converter
The Analog-to-Digital Converter (ADC) module uses a Successive Approximation Register (SAR)
architecture to deliver a 12-bit, low-power, high-precision conversion value. The successive
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April 25, 2012
Texas Instruments-Advance Information