TMS320C6657CZH Datasheet, PDF (72/233 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

TMS320C6655/57
Fixed and Floating-Point Digital Signal Processor
SPRS814A—August 2012
3.3.3 JTAG ID (JTAGID) Register Description
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The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the device, the
JTAG ID register resides at address location 0x0262 0018. The JTAG ID Register is shown in Figure 3-3 and
described in Table 3-5.
Figure 3-3 JTAG ID (JTAGID) Register
31
28
27
12
11
1
0
VARIANT
PART NUMBER
MANUFACTURER
LSB
R-xxxxb
R-1011 1001 0111 1010b
0000 0010 111b
R-1
Legend: RW = Read/Write; R = Read only; -n = value after reset
Table 3-5
JTAG ID Register Field Descriptions
Bit Field
31-28 VARIANT
27-12 PART NUMBER
11-1 MANUFACTURER
0
LSB
End of Table 3-5
Value
xxxxb
1011 1001 0111 1010b
0000 0010 111b
1b
Description
Variant (4-Bit) value.
Part Number for boundary scan
Manufacturer
This bit is read as a 1 for TMS320C6655/57
Note—The value of the VARIANT and PART NUMBER fields depend on the silicon revision. See the Silicon
Errata for details.
3.3.4 Kicker Mechanism (KICK0 and KICK1) Register
The Bootcfg module contains a kicker mechanism to prevent any spurious writes from changing any of the Bootcfg
MMR values. When the kicker is locked (which it is initially after power on reset), none of the Bootcfg MMRs are
writable (they are only readable). On the C6655/57, the exception to this are the IPC registers such as IPCGRx and
IPCARx. These registers are not protected by the kicker mechanism. This mechanism requires two MMR writes to
the KICK0 and KICK1 registers with exact data values before the kicker lock mechanism is un-locked. See
Table 3-2 ‘‘Device State Control Registers’’ on page 67 for the address location. Once released, then all the Bootcfg
MMRs having write permissions are writable (the read only MMRs are still read only). The first KICK0 data is
0x83e70b13. The second KICK1 data is 0x95a4f1e0. Writing any other data value to either of these kick MMRs will
lock the kicker mechanism and block any writes to Bootcfg MMRs. To ensure protection of all Bootcfg MMRs,
software must always re-lock the kicker mechanism after completing the MMR writes.
3.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
The LRSTNMIPINSTAT Register is created in Boot Configuration to latch the status of LRESET and NMI based on
CORESEL. The LRESETNMI PIN Status Register is shown and described in the following tables.
Figure 3-4 LRESETNMI PIN Status Register (LRSTNMIPINSTAT)
31
18
17
16
15
2
1
0
Reserved
NMI1/Reserved
NMI0
Reserved
LR1
LR0
R, +0000 0000
R-0
R-0
R, +0000 0000
R-0
R-0
Legend: R = Read only; -n = value after reset;
72 Device Configuration
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