TMS320C6202_16 Datasheet, PDF (72/110 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6202, TMS320C6202B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104I -- OCTOBER 1999 -- REVISED FEBRUARY 2004
EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)
Setup = 2 Strobe = 3 Hold = 2
CLKOUT1
XCEx
1
2
XBE[3:0]/
XA[5:2]^†
XD[31:0]
XOE
XRE
XWE/XWAIT^‡
1
1
6
7
2
3
4
2
5
XRDY^§
† _{XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.}
‡ _{XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses.}
§ _{XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.}
Figure 37. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Not Used)
Setup = 2 Strobe = 3
Not Ready
Hold = 2
CLKOUT1
1
2
XCEx
XBE[3:0]/
1
XA[5:2]^†
XD[31:0]
2
3
4
XOE
XRE
1
2
8
10
9
XWE/XWAIT^‡
11
XRDY^§
† _{XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.}
‡ _{XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses.}
§ _{XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.}
Figure 38. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Used)
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