TVP5145 Datasheet, PDF (70/94 Pages) Texas Instruments – NTSC/PAL/SECAM/Component Digital Video Decoder With Macrovision™ Detection

2.12.51 Interrupt Status Register A
Address
C0h
7
Lock state
interrupt
6
Lock interrupt
5
Cycle complete
interrupt
4
Bus error
interrupt
3
Reserved
2
FIFO threshold
interrupt
1
Line interrupt
0
Data interrupt
The interrupt status register A can be polled by the host processor to determine the source of an interrupt. After an
interrupt condition is set it can be reset by writing to this register with a 1 in the appropriate bit(s).
Lock state interrupt:
0 = TVP5145 not locked to video signal
1 = TVP5145 locked to video signal
Lock interrupt:
0 = A transition has not occurred on the lock signal
1 = A transition has occurred on the lock signal
Cycle complete interrupt:
0 = Read or write cycle in progress
1 = Read or write cycle complete
Bus error interrupt:
0 = No bus error
1 = PHI interface detected an illegal access
FIFO threshold interrupt:
0 = The amount of data in the FIFO has not yet crossed the threshold programmed at address C8h.
1 = The amount of data in the FIFO has crossed the threshold programmed at address C8h.
Line interrupt:
0 = The video line number has not yet been reached.
1 = The video line number programmed in address CAh has occurred.
Data interrupt:
0 = No data is available
1 = VBI data is available either in the FIFO or in the VBI data registers.
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