TSC2017 Datasheet, PDF (7/38 Pages) Texas Instruments – 12-Bit, Nanopower, 4-Wire Micro TOUCH SCREEN CONTROLLER with I2C™ Interface

TSC2017
www.ti.com
TIMING REQUIREMENTS: I²C Fast Mode (SCL = 400kHz)
All specifications typical at –40°C to +85°C, V_DD = 1.6V, unless otherwise noted.
TWO-WIRE FAST MODE PARAMETERS
TEST CONDITIONS
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition
Low period of SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
Data setup time
Rise time for both SDA and SCL signals (receiving)
Fall time for both SDA and SCL signals (receiving)
Fall time for both SDA and SCL signals (transmitting)
Setup time for STOP condition
Capacitive load for each bus line
Cycle time
8 bits
12 bits
Effective throughput
8 bits
12 bits
Equivalent rate = effective throughput × 7
8 bits
12 bits
f_SCL
t_BUF
t_{HD, STA}
t_LOW
t_HIGH
t_{SU, STA}
t_{HD, DAT}
t_{SU, DAT}
t_R
t_F
t_F
t_{SU, STO}
C_b
C_b = total bus capacitance
C_b = total bus capacitance
C_b = total bus capacitance
C_b = total capacitance of one bus line in pF
40 SCL + 127 CCLK, V_DD = 1.8V
49 SCL + 148 CCLK, V_DD = 1.8V
V_DD = 1.8V
V_DD = 1.8V
V_DD = 1.8V
V_DD = 1.8V
SBAS472 – DECEMBER 2009
MIN
0
1.3
0.6
1.3
0.6
0.6
0
100
20+0.1×C_b
20+0.1×C_b
20+0.1×C_b
0.6
TYP
134.7
203.4
7.42
4.92
51.97
34.42
MAX UNIT
400 kHz
μs
μs
μs
μs
μs
0.9 μs
ns
300 ns
300 ns
250 ns
μs
400 pF
μs
μs
kSPS
kSPS
kHz
kHz
TIMING REQUIREMENTS: I²C High-Speed Mode (SCL = 1.7MHz)
All specifications typical at –40°C to +85°C, V_DD = 1.6V, unless otherwise noted.
TWO-WIRE HIGH-SPEED MODE PARAMETERS
TEST CONDITIONS
SCL clock frequency
Hold time (repeated) START condition
Low period of SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
Data setup time
Rise time for SCL signal (receiving)
Rise time for SDA signal (receiving)
Fall time for SCL signal (receiving)
Fall time for SDA signal (receiving)
Fall time for both SDA and SCL signals (transmitting)
Setup time for STOP condition
Capacitive load for each bus line
Cycle time
8 bits
12 bits
Effective throughput
8 bits
12 bits
Equivalent rate = effective throughput × 7
8 bits
12 bits
f_SCL
t_{HD, STA}
t_LOW
t_HIGH
t_{SU, STA}
t_{HD, DAT}
t_{SU, DAT}
t_R
t_R
t_F
t_F
t_F
t_{SU, STO}
C_b
C_b = total bus capacitance
C_b = total bus capacitance
C_b = total bus capacitance
C_b = total bus capacitance
C_b = total bus capacitance
C_b = total capacitance of one bus line in pF
40 SCL + 127 CCLK, V_DD = 1.8V
49 SCL + 148 CCLK, V_DD = 1.8V
V_DD = 1.8V
V_DD = 1.8V
V_DD = 1.8V
V_DD = 1.8V
MIN TYP MAX UNIT
0
1.7 MHz
160
ns
320
ns
120
ns
160
ns
0
150 ns
10
ns
20
80 ns
20
160 ns
20
80 ns
20
160 ns
20
160 ns
160
ns
400 pF
58.2
μs
109.7
μs
17.17
kSPS
9.12
kSPS
120.22
kHz
63.81
kHz
Copyright © 2009, Texas Instruments Incorporated
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