TPS99110-Q1_17 Datasheet, PDF (7/67 Pages) Texas Instruments – System-Basis Chip for Automotive Applications

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TPS99110-Q1
SLIS155A – OCTOBER 2014 – REVISED MARCH 2015
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
V_VIN
V_VIO
Input supply voltage
VIO pin Input voltage
Full functionality, wakeup from standby mode
requires 5.5-V V_VIN minimum
MIN
NOM
MAX UNIT
5.2
38.5
V
3
5.5 V
6.4 Thermal Information
THERMAL METRIC⁽¹⁾
PAP (HTQFP)
64 PINS
UNIT
R_θJA
R_θJC(top)
R_θJB
ψ_JT
ψ_JB
R_θJC(bot)
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
24.2
9.1
7.5
°C/W
0.2
7.4
0.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Range of Functionality
Functionality remains the same for all functional blocks including the block affected by a short- circuit or test pulse event.
These affected blocks can be: K/LIN and CAN transceivers, current-loop interface, operational amplifier, sensor supplies. T_C
= –40°C to 150°C, T_J = –40°C to 175°C unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
All functions are operational in this voltage range.
Wakeup from standby mode requires VIN minimum of
5.5 V
5.2
38.5
V_VIN
Input voltage, VIN
NRST5 might output a low level, but NRST3 outputs a
high level, VDD5 must be above 3.3 V, ENDRV or
NENDRV must be inactive
Wakeup from standby mode requires VIN minimum of
5.5 V
V
4
5.2
I_Q(STBY)
I_{IN_IDLE}
V_VIO
V_{DIGIN_HIGH}
Quiescent current in standby modes, ENA,
PWL_WD = Low⁽¹⁾
Input current in enabled mode
VIO voltage range
Digital input high threshold,KL_TXD,
CAN_TXD, SDI, CLK, NCS, PWL_WD,
NRESTART, NWDDIS
V_IN = 16 V and T_J < 70°C
V_IN = 28 V and T_J < 175°C
No external current consumption
50
µA
400
µA
15
mA
3
5.5
V
2
V
V_{DIGIN_LOW}
Digital input low threshold, KL_TXD,
CAN_TXD, SDI, CLK, NCS, PWL_WD,
NRESTART, NWDDIS
0.8
V
V_{DIGIN_HYST}
Digital input Hysteresis, KL_TXD,
CAN_TXD, SDI, CLK, NCS, PWL_WD,
NRESTART, NWDDIS
0.1
V
I_{DIG_LEAK}
Digital input leakage current, CAN_TXD,
SDI, CLK, NCS, PWL_WD, NRESTART,
NWDDIS
0 V < V_LEAK ≤ 5.5 V
–60
60
µA
I_{KL_TXD_LEAK} KL_TXD leakage current
V_{DIGOUT_HIGH}
Digital output high level, KL_RXD,
CAN_RXD, SDO, CLSS_OUTx
0 V < V_LEAK ≤ 5.5 V
I_OUT = –2 mA
–300
V_VIO – 0.2
300
µA
V
V_{DIGOUT_LOW}
Digital output low level, KL_RXD,
CAN_RXD, SDO, CLSS_OUTx
I_OUT = 2 mA
0.2
V
V_{SENSOR_IN} Forced voltage at SENSOR_IN pin
I_{WAKE_LEAK} Leakage current, WAKE pin
I_{REV_ENA}
Digital output high level, KL_RXD,
CAN_RXD, SDO, CLSS_OUTx
V_VIN = 16 V and T_J < 70°C
V_VIN = 28 V and T_J < 175°C
Functionality remains the same for all functional
blocks:
40
V
1.5
µA
15
–5
5
mA
(1) Sum of current into VIN and WAKE.
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