TPS62097 Datasheet, PDF (7/28 Pages) Texas Instruments – TPS62097 2-A High Efficiency Step-Down Converter with iDCS-Control, Forced PWM Mode and Selective Switching Frequency

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8 Detailed Description
TPS62097
SLVSCD6 – DECEMBER 2015
8.1 Overview
The TPS62097 synchronous step-down converter is based on the iDCS-Control (Industrial Direct Control with
Seamless transition into Power Save Mode) topology. The control topology not only keeps the advantages of
DCS-Control, but also provides other features:
• Forced PWM mode over the whole load range
• Selectable PWM switching frequency
• 1% output voltage accuracy
• Output voltage sequencing and tracking
The iDCS-Control topology operates in PWM (Pulse Width Modulation) mode for medium to heavy load
conditions and in Power Save Mode (PSM) at light load conditions. Or it forces the device in fixed frequency
PWM mode only operation for the whole load range.
In PWM mode, the device operates with a predictive On-time switching pulse. A quasi-fixed switching frequency
over the input and output voltage range is achieved by using an input and output voltage feed forward to set the
on-time, as shown in Table 1. The converter enters Power Save Mode, reducing the switching frequency and
minimizing current consumption, to achieve high efficiency over the entire load current range. Since iDCS-Control
supports both operation modes within a single building block, the transition from PWM mode to Power Save
Mode is seamless and without effects on the output voltage.
8.2 Functional Block Diagram
AVIN
PG
EN
AGND
SS/TR
MODE
V_FB
V_REF
Bandgap
375kΩ⁽²⁾ _{Undervoltage Lockout}
Thermal Shutdown
V_IN
Hiccup
Counter
High-side
Current Sense
Low-side
Current Sense
MOSFET Driver
Control Logic
Voltage V_REF
Clamp
V_IN
On time
Selection
t_ON
Timer
Ramp
Comparator
Direct Control
and
Compensation
iDCS - Control
Error Amplifier
V_REF
PVIN
SW
PGND
R1⁽¹⁾
R2⁽¹⁾
VOS
FB
165Ω
Note:
(1) R1, R2 are implemented in the fixed output voltage versions only.
(2) When the device is enabled, the 375 kΩ resistor is disconnected.
EN Output Discharge
Logic
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