TPS51513_16 Datasheet, PDF (7/39 Pages) Texas Instruments – SINGLE PHASE, D-CAP SYNCHRONOUS BUCK CONTROLLER

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TPS51513
(Top View)
TPS51513
SLUS956A – JUNE 2009 – REVISED FEBRUARY 2010
GND
CSP
CSN
GSNS
VSNS
REF
IMON2
IMON
32 31 30 29 28 27 26 25
1
24 PG
2
23 PGOOD
3
22 PGND
4
21 V5IN
5
PowerPAD^TM
20 DRVL
6
19 LL
7
18 VBST
8
17 DRVH
9 10 11 12 13 14 15 16
PIN # NAME
3 CSN
2 CSP
31 DROOP
17 DRVH
20 DRVL
25 EN
1 GND
4 GSNS
8 IMON
7 IMON2
12 IMONC
29 ISLEW
19 LL
10
11 NC
13
28 OSRSEL
24 PG
22 PGND
23 PGOOD
Table 1. Pin Functions
I/O DESCRIPTION
I
Negative current sense input. Connect to the negative node of current sense resistor or inductor DCR sense
RC network.
I
Positive current sense input. Connect to the positive node of current sense resistor or inductor DCR sense
RC network.
O
Output of g_M error amplifier. A resistor to VREF sets the droop gain. A capacitor to VREF helps shape the
transient response. Please see Applications Information section for configurations with no droop.
O Top N-channel FET gate drive outputs.
O Synchronous N-channel FET gate drive outputs.
I Chip enable signal. 1-V I/O level; 100-ns de-bounce. Regulator enters controlled soft-stop when brought low.
— Analog / signal ground. Tie to quiet ground plane.
I
Voltage sense return tied directly to GND of the microprocessor. Tie to GND with a 10-Ω resistor for
feedback when mP is not present.
O
Current monitor output. The current out of the IMON output is proportional to the voltage between the CS
inputs.
O Connection point for IMON mirror matching resistor.
I
Clamp reference input for the IMON signal; 3.6-V maximum. Bypass to GND with a ceramic capacitor of 0.1
mF or greater.
I
Precision current set-point for slew rate control. Tie the ISLEW resistor to GND to select the low range of
OCP values; VREF for the higher range.
I/O Top N-channel FET gate drive return. Also, input for adaptive gate drive timing.
— No connection; leave floating.
I
Overshoot reduction (OSR) setting. One of three OSR settings is selected with OSRSEL = GND/VREF/3.3
V. OSRSEL = 5 V disables OSR.
O
Negative active power good output. Transitions low of approximately 50 ms after V_CORE reaches the
VID-defined level. Open-drain. Leave open if unused.
— Power return for the synchronous N-channel FET gate driver outputs.
O Power Good output. 6-ms nominal delay from PG. Open-drain.
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