TMS27C040_08 Datasheet, PDF (7/12 Pages) Texas Instruments – PROGRAMMABLE READ-ONLY MEMORY

TMS27C040 524288 BY 8ĆBIT UV ERASABLE
TMS27PC040 524288 BY 8ĆBIT
PROGRAMMABLE READĆONLY MEMORY
SMLS040F − NOVEMBER 1990 − REVISED SEPTEMBER 1997
switching characteristics over recommended ranges of operating conditions (see Notes 3
and 4)
PARAMETER
TEST CONDITIONS
’27C040-10
’27 PC040-10
MIN MAX
’27C040-12
’27 PC040-12
MIN MAX
’27C040-15
’27 PC040-15
MIN MAX
UNIT
ta(A)
ta(E)
ten(G)
tdis
Access time from address
Access time from chip enable
Output enable time from G
Output disable time from G or E, whichever
occurs first
Output data valid time after change of
tv(A) _{address, E, or G, whichever occurs firstâ€} 
CL = 100 pF,
1 Series 74
TTL load,
Input tr ≤ 20 ns,
Input tf ≤ 20 ns
100
100
50
0 50
0
120
120
50
0 50
0
150 ns
150 ns
50 ns
0 50 ns
0
ns
† _{Value calculated from 0.5-V delta to measured output level.}
NOTES: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low. (See Figure 2)
4. Common test conditions apply for tdis except during programming.
switching characteristics for programming: V_CC = 6.5 V and V_PP = 13 V (SNAP! Pulse), T_A = 25°C
(see Note 3)
PARAMETER
MIN MAX UNIT
tdis(G) Output disable time from G
0 100 ns
ten(G) Output enable time from G
150 ns
NOTE 3: For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low. (See Figure 2)
timing requirements for programming
tw(PGM)
tsu(A)
tsu(E)
tsu(G)
tsu(D)
tsu(VPP)
tsu(VCC)
th(A)
th(D)
Pulse duration, program
Setup time, address
Setup time, E
Setup time, G
Setup time, data
Setup time, VPP
Setup time, VCC
Hold time, address
Hold time, data
SNAP! Pulse programming algorithm
MIN NOM
95 100
2
2
2
2
2
2
0
2
MAX
105
UNIT
µs
µs
µs
µs
µs
µs
µs
µs
µs
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