SN74LV1T04DCKR Datasheet, PDF (7/16 Pages) Texas Instruments – Single Power Supply Inverter Gate CMOS Logic Level Shifter

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SN74LV1T04
SCLS738A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
C_L
(see Note A)
1 MΩ
LOAD CIRCUIT
C_L
V_MI
V_MO
V_CC = 2.5 V
± 0.2 V
5, 10, 15, 30 pF
V_I/2
V_CC/2
V_CC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
V_I/2
V_CC/2
Input
V_I
V_MI
V_MI
0V
t_PLH
Output
t_PHL
V_MO
t_PHL
V_Mo
V_OH
V_OL
t_PLH
Output
V_Mo
V_Mo
V_OH
V_OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. C_L includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O = 50 Ω, slew rate ≥ 1 V/ns.
C. The outputs are measured one at a time, with one transition per measurement.
D. t_PLH and t_PHL are the same as t_pd.
Figure 6. Load Circuit and Voltage Waveforms
MORE PRODUCT SELECTION
DEVICE
SN74LV1T00
SN74LV1T02
SN74LV1T04
SN74LV1T08
SN74LV1T17
SN74LV1T14
SN74LV1T32
SN74LV1T50
SN74LV1T86
SN74LV1T125
SN74LV1T126
SN74LV4T125
PACKAGE
DCK, DBV
DCK, DBV
DCK, DBV
DCK, DBV
DCK, DBV
DCK, DBV
DCK, DBV
DCK, DBV
DCK, DBV
DCK, DBV
DCK, DBV
RGY, PW
DESCRIPTION
2-Input Positive-NAND Gate
2-Input Positive-NOR Gate
Inverter Gate
2-Input Positive-AND Gate
Single Buffer Gate with 3-state Output
Single Schmitt-Trigger Inverter Gate
2-Input Positive-OR Gate
Single Buffer Gate with 3-state Output
Single 2-Input Exclusive-Or Gate
Single Buffer Gate with 3-state Output
Single Buffer Gate with 3-state Output
Quadruple Bus Buffer Gate With 3-State Outputs
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